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ds07-16308-1e fujitsu semiconductor data sheet 32-bit risc microcontroller cmos fr30 series mb91133/mb91f133 n description the mb91133/mb91f133, a standard single-chip microcontroller featuring various i/o resources and bus control mechanisms to incorporate the control required for high-performance high-speed cpu processes, is the core unit in the 32-bit risc cpu (fr family) . this unit has the optimal specifications for incorporating applications that require high-performance cpu pro- cessing power by featuring peripheral i/o resources suitable for single-lens reflex cameras, digital video cameras, etc. n features 1. cpu ? 32-bit risc (fr30) , load/store architecture, 5-level pipeline ? multi-purpose register : 32 bits 16 ? 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle ? instructions for barrel shift, bit processing and inter-memory transfers : instructions suited to loading purposes ? function entry / exit instruction, multi load / store instruction of register details : high-level language handling instruction ? register interlock function : simplification of assembler description ? branch instruction with delay slot : reduction in overheads in case of branching ? multiplier is built-in / supported at instruction level. ? signed 32-bit multiplication : 5 cycles ? signed 16-bit multiplication : 3 cycles ? interruption (saving pc and ps) : 6 cycles, 16 priority levels (continued) n packages 144-pin plastic fbga 144-pin plastic lqfp (bga-144p-m01) (fpt-144p-m08)
mb91133/mb91f133 2 (continued) 2. bus interface ? 24-bit address output, 8/16-bit data input/output ? basic bus cycle : 2 clock cycles ? interface support for various memories ? unused data and address pins can be used as input/output ports. ? supports little endian mode 3. built-in rom mask device : 254 kb; flash device : 254 kb; eva-flash device : 254 kb 4. built-in ram mask device : 8 kb; flash device : 8 kb; eva-flash device : 8 kb 5. dma controller this is a descriptor-type ma controller whose transfer parameters are arranged in the main memory. a maximum of 8 factors in total (internal and external) can be transferred. external factors are 3 channels. 6. bit search module searches the first 1 / 0 change bit positions within 1 cycle from msb in 1 word 7. timer ? 16-bit reload timer 5 channels ? 16-bit ocu 8 channels, icu 4 channels, free-run timer 1 channel output waveform adjusting function for ac motor waveforms is included in the above timer. ? 8/16-bit up/down timer/counter (8-bit 2 channels or 16-bit 1 channel) external interruption and pin are shared for ain and bin. ? 16-bit down count timer 5 channels; can also be used as the uart baud rate timer ? 16-bit ppg timer 6 channels; out-pulse cycle / duty can be changed at random 8. d/a converter ?8-bit 3 channels 9. a/d converter (sequential comparison type) ? 10-bit 8 channels ? sequential conversion method (conversion time 5.0 m s at 33 mhz) ? setting for single conversion, scan conversion and repeat conversion is possible. ? conversion starting function using hardware or software 10. serial i/o ?uart 5 channels; clock synchronous serial transfer with lsb / msb switching function is possible for both. ? serial data output or serial lock output can be selected using push-pull / open-drain software. 11. level comparator input ? 1 channel; shared input and pins of a/d converter. 12. clock switching function ? base clock : software can be used to select from two types of clock sources, namely 32 khz and high-speed. ? gear function : four types of settings (1 : 1, 1 : 2, 1 : 4, 1 : 8) can be set individually as the operating clock ratio to the basic clock per cpu and peripheral equipment.
mb91133/mb91f133 3 13. interruption controller ? external interruption input (total 24 channels) ? with pull up pin control / standby return function : 4 channels (rising / falling / h level / l level settings are possible) ? with pull up pin control / standby return function; ain / bin pins of the up/down counter are shared : 4 channels (rising / falling / h level / l level settings are possible) ? with pull up pin controln : 16 channels (rising / falling / h level / l level settings are possible) ? internal interruption factor ? interruption / delay interruption by resource 14. others ? reset factors power on reset, watchdog timer, software reset, external reset ? low power consumption mode sleep/stop mode ? packages fbga-144, lqfp-144 ? cmos technology (0.35 m m) ? power two power sources (5 v / 3 v) 1) 5 v system : 5 v 10 % (a/d, d/a and level comparator included) 2) 3 v system : a) 3.0 v to 3.6 v : all functions guaranteed b) 2.7 v to 3.0 v : all functions guaranteed for single-chip mode of mask devices only n product lineup mb91133 mb91f133 mb91fv130 classification mask rom device (mass production item) flash rom device (for evaluation) piggy/eva device (for evaluation / development) ram capacity 6 kb 6 kb 6 kb crom capacity 254 kb ?? flash capacity ? 254 kb 254 kb cram capacity 2 kb 2 kb 2 kb others mass production trial production provided
mb91133/mb91f133 4 n pin assignments ? mb91fv130 (bottom view) (pga-299c-a01) 3 2 5 8 25 27 32 34 22 29 37 50 53 45 49 52 57 68 71 74 299 296 293 277 274 270 268 278 275 262 254 247 257 252 250 245 233 230 224 298 292 289 286 283 280 276 269 264 263 258 251 248 243 240 237 234 225 221 10 4 297 291 287 284 279 271 265 261 256 249 242 239 235 229 228 219 218 13 6 300 295 290 285 281 272 267 259 255 246 241 236 231 226 223 215 207 16 11 7 1 294 288 282 273 266 260 253 244 238 232 227 222 217 212 202 19 15 12 9 220 216 213 209 199 23 18 17 14 214 211 210 205 195 26 24 21 20 208 206 204 201 203 33 31 30 28 198 197 196 194 200 39 38 35 36 192 193 191 190 187 40 41 43 42 186 185 188 189 179 44 46 47 48 178 180 181 183 172 51 54 56 58 170 171 174 176 184 55 60 61 64 164 167 168 173 182 59 63 66 70 159 162 165 169 177 62 67 72 77 82 88 94 103 110 116 123 133 139 145 153 157 161 166 175 65 73 76 81 86 91 96 105 109 117 122 131 136 141 147 151 156 163 158 69 78 79 85 89 92 99 106 111 115 121 129 135 138 142 148 154 160 155 75 84 87 90 93 98 101 108 113 114 119 126 130 134 137 140 144 150 152 80 83 95 100 102 107 97 104 112 125 128 118 120 124 127 132 143 146 149
mb91133/mb91f133 5 ? mb91f133/mb91133 (top view) (bga-144p-m01) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 abcdefghj klmnp index 108 107 106 110 109 105 111 112 113 102 103 104 99 100 101 96 97 98 95 92 93 91 94 89 88 90 85 84 86 82 81 83 79 78 80 75 76 77 74 73 69 72 71 70 87 115 114 116 118 117 119 121 120 122 125 124 126 123 128 129 127 130 132 133 134 131 135 136 137 138 139 140 142 141 5 8 143 1 4 6 144 2 3 7 11 9 10 14 12 13 18 15 16 17 19 22 21 20 26 23 25 24 29 28 27 32 31 30 41 44 47 50 54 51 55 58 62 65 68 59 33 34 40 42 45 48 52 57 61 64 67 37 35 39 43 46 49 53 56 60 63 66 38 36
mb91133/mb91f133 6 ? mb91f133/mb91133 (top view) (fpt-144p-m08) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 p20/d16 p21/d17 p22/d18 p23/d19 p24/d20 p25/d21 p26/d22 p27/d23 v ss p30/d24 p31/d25 p32/d26 p33/d27 p34/d28 p35/d29 p36/d30 p37/d31 p40/a00 p41/a01 p42/a02 p43/a03 p44/a04 p45/a05 p46/a06 p47/a07 v ss v cc 5 p50/a08 p51/a09 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 p60/a16/int16 md2 md1 md0 v ss x1 x0 v cc 3 x1a x0a v ss rst pl7/dack2 pl6/dreq2 pl5/deop1 pl4/dack1 pl3/dreq1 pl2/deop0 pl1/dack0 pl0/dreq0 pk7/an7/cmp pk6/an6 pk5/an5 pk4/an4 pk3/an3 pk2/an2 pk1/an1 pk0/an0 av ss avrl avrh av cc davc davs da0 da1 da2 v cc 5 ph0/sin0 ph1/sot0 ph2/sck0 pi0/sin1 pi1/sot1 pi2/sck1 pi3/sin2 pi4/sot2 pi5/sck2 pj0/sin3 pj1/sot3 pj2/sck3 pj3/sin4 pj4/sot4 pj5/sck4 v cc 3 v ss pg5/ppg5 pg4/ppg4 pg3/ppg3 pg2/ppg2 pg1/ppg1 pg0/ppg0 pf7/rto7 pf6/rto6 pf5/rto5 pf4/rto4 pf3/rto3 pf2/rto2 pf1/rto1 pf0/rto0 pe7/dtti pe6/frck pe5/in3 pe4/in2 p61/a17/int17 p62/a18/int18 p63/a19/int19 p64/a20/int20 p65/a21/int21 p66/a22/int22 p67/a23/int23 v cc 3 p80/rdy p81/bgrnt p82/brq p83/rd p84/wr0 p85/wr1 p86/clk v ss pc0/int0 pc1/int1 pc2/int2 pc3/int3 pc4/ain0/int4 pc5/bin0/int5 pc6/ain1/int6 pc7/bin1/int7 pd0/int8/trg0 pd1/int9/trg1 pd2/int10/trg2 pd3/int11/trg3 pd4/int12/trg4 pd5/int13/trg5 pd6/deop2/int14 pd7/atg/int15 pe0/zin0 pe1/zin1 pe2/in0 pe3/in1
mb91133/mb91f133 7 n pin numbers list ? device : mb91fv130 package : pga-299c-a01 (continued) no. pin name no. pin name no. pin name no. pin name 1 p20/d16 35 p54/a12 69 n.c. 103 pk3/an3 2v ss 36 p55/a13 70 n.c. 104 v cc 5 3open37v cc 571 v ss 105 pk4/an4 4 p21/d17 38 p56/a14 72 n.c. 106 pk5/an5 5v cc 5 39 p57/a15 73 n.c. 107 pk6/an6 6 p22/d18 40 p60/a16/int16 74 v cc 5 108 pk7/an7/cmp 7 p23/d19 41 p61/a17/int17 75 n.c. 109 davc 8v ss 42 p62/a18/int18 76 md0 110 davs 9 p24/d20 43 p63/a19/int19 77 md1 111 da0 10 p25/d21 44 p64/a20/int20 78 md2 112 v ss 11 p26/d22 45 p65/a21/int21 79 v cc 3113da1 12 p27/d23 46 p66/a22/int22 80 v ss 114 da2 13 p30/d24 47 p67/a23/int23 81 x0 115 ph0/sin0 14 p31/d25 48 p80/rdy 82 x1 116 ph1/sot0 15 p32/d26 49 v cc 383v cc 5 117 ph2/sck0 16 p33/d27 50 v ss 84 rst 118 pi0/sin1 17 p34/d28 51 p81/bgrnt 85 n.c. 119 pi1/sot1 18 p35/d29 52 p82/brq 86 iclk 120 pi2/sck1 19 p36/d30 53 v cc 587ics0121pi3/sin2 20 p37/d31 54 p83/rd 88 ics1 122 pi4/sot2 21 p40/a00 55 p84/wr0 89 ics2 123 pi5/sck2 22 v cc 5 56 p85/wr1 90 icd0 124 pj0/sin3 23 p41/a01 57 p86/clk 91 icd1 125 v cc 5 24 p42/a02 58 pl0/dreq0 92 icd2 126 pj1/sot3 25 p43/a03 59 pl1/dack0 93 icd3 127 pj2/sck3 26 p44/a04 60 pl2/deop0 94 break 128 v ss 27 p45/a05 61 pl3/dreq1 95 av cc 129 v cc 3 28 p46/a06 62 pl4/dack1 96 avrh 130 x0a 29 v ss 63 pl5/deop1 97 v ss 131 x1a 30 p47/a07 64 pl6/dreq2 98 avrl 132 v ss 31 p50/a08 65 pl7/dack2 99 av ss 133 pj3/sin4 32 p51/a09 66 n.c. 100 pk0/an0 134 pj4/sot4 33 p52/a10 67 n.c. 101 pk1/an1 135 pj5/sck4 34 p53/a11 68 v cc 5 102 pk2/an2 136 pc0/int0
mb91133/mb91f133 8 (continued) no. pin name no. pin name no. pin name no. pin name no. pin name 137 pc1/int1 173 pf5/rto5 209 tad14 245 tdt23 281 tdt53 138 pc2/int2 174 pf6/rto6 210 tad15 246 tdt24 282 tdt54 139 pc3/int3 175 pf7/rto7 211 v cc 3247 v ss 283 tdt55 140 pc4/int4/ain0 176 pg0/ppg0 212 toe 248 tdt25 284 tdt56 141 pc5/int5/bin0 177 pg1/ppg1 213 tce1 249 tdt26 285 tdt57 142 pc6/int6/ain1 178 pg2/ppg2 214 tadsc 250 tdt27 286 v cc 3 143 v cc 5 179 v ss 215 twr 251 tdt28 287 tdt58 144 pc7/int7/bin1 180 pg3/ppg3 216 tdt00 252 tdt29 288 tdt59 145 pd0/int8/trg0 181 pg4/ppg4 217 tdt01 253 tdt30 289 tdt60 146 v ss 182 pg5/ppg5 218 v ss 254 v cc 5290tdt61 147 pd1/int9/trg1 183 n.c. 219 tdt02 255 tdt31 291 tdt62 148 pd2/int10/trg2 184 n.c. 220 tdt03 256 tdt32 292 tdt63 149 v cc 5 185 n.c. 221 v cc 5 257 tdt33 293 v cc 5 150 pd3/int11/trg3 186 n.c. 222 tdt04 258 tdt34 294 tdt64 151 pd4/int12/trg4 187 v cc 5 223 tdt05 259 tdt35 295 tdt65 152 v ss 188 exram 224 v ss 260 tdt36 296 v ss 153 pd5/int13/trg5 189 tad00 225 tdt06 261 tdt37 297 tdt66 154 pd6/int14/deop2 190 tad01 226 tdt07 262 v ss 298 tdt67 155 v cc 5 191 tad02 227 tdt08 263 tdt38 299 v cc 5 156 pd7/int15/atg 192 tad03 228 tdt09 264 tdt39 300 tdt68 157 pe0/zin0 193 v cc 3 229 tdt10 265 tdt40 158 v ss 194 tad04 230 v cc 5266tdt41 159 pe1/zin1 195 tad05 231 tdt11 267 tdt42 160 pe2/in0 196 tad06 232 tdt12 268 tdt43 161 pe3/in1 197 tad07 233 v ss 269 v cc 3 162 pe4/in2 198 tad08 234 tdt13 270 tdt44 163 pe5/in3 199 tad09 235 tdt14 271 tdt45 164 pe6/frck 200 v ss 236 tdt15 272 tdt46 165 pe7/dtti 201 tad10 237 tdt16 273 tdt47 166 v cc 3 202 tad11 238 tdt17 274 tdt48 167 pf0/rto0 203 v cc 5 239 tdt18 275 v cc 5 168 pf1/rto1 204 tad12 240 v cc 3276tdt49 169 pf2/rto2 205 tad13 241 tdt19 277 tdt50 170 pf3/rto3 206 tad14 242 tdt20 278 v ss 171 pf4/rto4 207 tad15 243 tdt21 279 tdt51 172 v cc 5 208 tclk 244 tdt22 280 tdt52
mb91133/mb91f133 9 ? device : mb91f133/mb91133 package : bga-144p-m01/fpt-144p-m08 (continued) lqfp fbga pin name lqfp fbga pin name lqfp fbga pin name 1 b2 p20/d16 36 p1 p60/a16/int16 71 p13 pe2/in0 2 b1 p21/d17 37 n2 p61/a17/int17 72 p14 pe3/in1 3 c1 p22/d18 38 p2 p62/a18/int18 73 n13 pe4/in2 4 c2 p23/d19 39 p3 p63/a19/int19 74 n14 pe5/in3 5 c3 p24/d20 40 n3 p64/a20/int20 75 m14 pe6/frck 6 d2 p25/d21 41 m3 p65/a21/int21 76 m13 pe7/dtti 7 d1 p26/d22 42 n4 p66/a22/int22 77 m12 pf0/rto0 8 d3 p27/d23 43 p4 p67/a23/int23 78 l13 pf1/rto1 9e2 v ss 44 m4 v cc 3 79 l14 pf2/rto2 10 e1 p30/d24 45 n5 p80/rdy 80 l12 pf3/rto3 11 e3 p31/d25 46 p5 p81/bgrnt 81 k13 pf4/rto4 12 f2 p32/d26 47 m5 p82/brq 82 k14 pf5/rto5 13 f1 p33/d27 48 n6 p83/rd 83 k12 pf6/rto6 14 f3 p34/d28 49 p6 p84/wr0 84 j13 pf7/rto7 15 g4 p35/d29 50 m6 p85/wr1 85 j14 pg0/ppg0 16 g2 p36/d30 51 l7 p86/clk 86 j12 pg1/ppg1 17 g1 p37/d31 52 n7 v ss 87 h11 pg2/ppg2 18 g3 p40/a00 53 p7 pc0/int0 88 h13 pg3/ppg3 19 h3 p41/a01 54 m7 pc1/int1 89 h14 pg4/ppg4 20 h1 p42/a02 55 m8 pc2/int2 90 h12 pg5/ppg5 21 h2 p43/a03 56 p8 pc3/int3 91 g12 v ss 22 h4 p44/a04 57 n8 pc4/ain0/int4 92 g14 v cc 3 23 j4 p45/a05 58 l8 pc5/bin0/int5 93 g13 pj5/sck4 24 j1 p46/a06 59 l9 pc6/ain1/int6 94 g11 pj4/sot4 25 j2 p47/a07 60 p9 pc7/bin1/int7 95 f11 pj3/sin4 26 j3 v ss 61 n9 pd0/int8/trg0 96 f14 pj2/sck3 27 k1 v cc 5 62 m9 pd1/int9/trg1 97 f13 pj1/sot3 28 k2 p50/a08 63 p10 pd2/int10/trg2 98 f12 pj0/sin3 29 k3 p51/a09 64 n10 pd3/int11/trg3 99 e14 pi5/sck2 30 l1 p52/a10 65 m10 pd4/int12/trg4 100 e13 pi4/sot2 31 l2 p53/a11 66 p11 pd5/int13/trg5 101 e12 pi3/sin2 32 l3 p54/a12 67 n11 pd6/deop2/int14 102 d14 pi2/sck1 33 m2 p55/a13 68 m11 pd7/atg /int15 103 d13 pi1/sot1 34 m1 p56/a14 69 n12 pe0/zin0 104 d12 pi0/sin1 35 n1 p57/a15 70 p12 pe1/zin1 105 c13 ph2/sck0
mb91133/mb91f133 10 (continued) lqfp fbga pin name lqfp fbga pin name 106 c14 ph1/sot0 126 c8 pl0/dreq0 107 b14 ph0/sin0 127 c7 pl1/dack0 108 a14 v cc 5 128 a7 pl2/deop0 109 b13 da2 129 b7 pl3/dreq1 110 a13 da1 130 d7 pl4/dack1 111 b12 da0 131 d6 pl5/deop1 112 a12 davs 132 a6 pl6/dreq2 113 c12 davc 133 b6 pl7/dack2 114 b11 av cc 134 c6 rst 115 a11 avrh 135 a5 v ss 116 c11 avrl 136 b5 x0a 117 b10 av ss 137 c5 x1a 118 a10 pk0/an0 138 a4 v cc 3 119 c10 pk1/an1 139 b4 x0 120 b9 pk2/an2 140 c4 x1 121 a9 pk3/an3 141 b3 v ss 122 c9 pk4/an4 142 a3 md0 123 d8 pk5/an5 143 a2 md1 124 b8 pk6/an6 144 a1 md2 125 a8 pk7/an7/cmp
mb91133/mb91f133 11 n pin descriptions (continued) pin no. pin name circuit type function 1 2 3 4 5 6 7 8 d16/p20 d17/p21 d18/p22 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 c external data bus bits 16 to 23 only valid for external bus 16-bit mode. can be used as ports in single-chip and external bus 8-bit modes. 10 11 12 13 14 15 16 17 d24/p30 d25/p31 d26/p32 d27/p33 d28p34 d29/p35 d30/p36 d31/p37 c external data bus bits 24 to 31 can be used as ports in single-chip mode. 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 a00/p40 a01/p41 a02/p42 a03/p43 a04/p44 a05/p45 a06/p46 a07/p47 a08/p50 a09/p51 a10/p52 a11/p53 a12/p54 a13/p55 a14/p56 a15/p57 f external address bus bits 0 to 15 valid for external bus mode. can be used as ports in single-chip mode. 36 37 38 39 40 41 42 43 a16/int16/p60 a17/int17/p61 a18/int18/p62 a19/int19/p63 a20/int20/p64 a21/int21/p65 a22/int22/p66 a23/int23/p67 o external address bus bits 16 to 23 [ int16 to 23 ] are external interruption request inputs 16 to 23. these inputs are always used when dealing with external interrup- tions is permitted, so output by ports should be stopped except when carried out intentionally. can be used as ports when address bus and external interruption request input are not used. 45 rdy/p80 c external rdy input this function is valid when external rdy input is permitted. 0 is input if the bus cycle being executed is not completed. can be used as a port when the external rdy input is not used.
mb91133/mb91f133 12 (continued) pin no. pin name circuit type function 46 bgrnt /p81 f external bus open reception output this function is valid when external bus open reception output is permitted. l is output if the external bus is opened. can be used as a port when the external bus open reception output is prohibit- ed. 47 brq/p82 c external bus open request input this function is valid when external bus open request input is per- mitted. 1 is input if the external bus requests to be opened. can be used as a port when the external bus open request input is not used. 48 rd /p83 f external bus read strobe output this function is valid when external bus read strobe output is per- mitted. can be used as a port when the external bus read strobe output is prohibited. 49 wr0 /p84 f external bus write strobe output this function is valid in external bus mode. can be used as a port in single-chip mode. 50 wr1 /p85 f external bus write strobe output this function is valid in external bus mode and with 16-bit buses. can be used as a port in single-chip mode or with external 8-bit bus. 51 clk/p86 f system clock output outputs the same clock frequency as the external bus operation. can be used as a port when it is not otherwise used. 53 54 55 56 int0/pc0 int1/pc1 int2/pc2 int3/pc3 h external interruption request inputs 0 to 3 these inputs are always used when dealing with external interrup- tions is permitted, so output by ports should be stopped except when carried out intentionally. can be used to reset standby as input is permitted in this port un- der standby status.can be used as ports when external interrup- tion request input is not used. 57 58 59 60 ain0/int4/pc4 bin0/int5/pc5 ain1/int6/pc6 bin1/int7/pc7 h external interruption request inputs 4 to 7 these inputs are always used when dealing with external interrup- tions is permitted, so output by ports should be stopped except when carried out intentionally. can be used to reset standby as in- put is permitted in these ports under standby status. [ ain, bin ] up/down timer input this input is always used when input is permitted, so output by ports should be stopped except when carried out intentionally. can be used as a port when external interruption request input and up/down timer input are not used.
mb91133/mb91f133 13 (continued) pin no. pin name circuit type function 61 62 63 64 65 66 67 68 trg0/int8/pd0 trg1/int9/pd1 trg2/int10/pd2 trg3/int11/pd3 trg4/int12/pd4 trg5/int13/pd5 deop2/int14/pd6 atg /int15/pd7 o external interruption request inputs 8 to 15 these inputs are always used when dealing with external interrup- tions is permitted, so output by ports should be stopped except when carried out intentionally. [ trg0 to 5 ] these are external trigger inputs for ppg timers. [ deop2 ] dma external transfer termination output this function is valid when external transfer termination output specification of the dma controller is permitted. [ atg ] a/d converter external trigger input these inputs are always used when they are selected as a/d initi- ation factors, so output by ports should be stopped except when carried out intentionally. can be used as ports when not otherwise used. 69 70 zin0/pe0 zin1/pe1 o up/down timer input these inputs are always used when input is permitted, so output by ports should be stopped except when carried out intentionally. can be used as ports when up/down timer input is not used. 71 72 73 74 in0/pe2 in1/pe3 in2/pe4 in3/pe5 f input capture input this function is valid when input capture activates input. can be used as ports when input capture input is not used. 75 frck/pe6 f external clock input pin of free-run timer can be used as a port when external clock input of free-run timer is not used. 76 dtti/pe7 f rton pin level fixed input invalid when input is permitted in the waveform generation area. can be used as a port when rton pin level fixed input is not used. 77 78 79 80 81 82 83 84 rto0/pf0 rto1/pf1 rto2/pf2 rto3/pf3 rto4/pf4 rto5/pf5 rto6/pf6 rto7/pf7 f output compare event pins/waveform output pins in the waveform generation area can be used as ports when specification of the output compare event pin/waveform output pin of the waveform generation area is prohibited. 85 86 87 88 89 90 ppg0/pg0 ppg1/pg1 ppg2/pg2 ppg3/pg3 ppg4/pg4 ppg5/pg5 f ppg timer output this function is valid when output specification of the ppg timer is permitted. can be used as ports when output specification of the ppg timer is prohibited. 111 110 109 da0 da1 da2 ? d/a converter output this function is valid when output specification of the d/a converter is permitted.
mb91133/mb91f133 14 (continued) pin no. pin name circuit type function 107 sin0/ph0 p uart0 data input this input is always used when uart0 activates input, so output by ports should be stopped except when carried out intentionally. can be used as a port when uart0 data input is not used. 106 sot0/ph1 p uart0 data output this function is valid when uart0 data output specification is per- mitted. can be used as a port when uart0 data output specifica- tion is prohibited. 105 sck0/ph2 p uart0 clock input/output this function is valid when uart0 clock output specification is per- mitted. can be used as a port when uart0 clock output specifi- cation is prohibited. 104 sin1/pi0 p uart1 data input this input is always used when uart1 activates input, so output by ports should be stopped except when carried out intentionally. can be used as a port when uart1 data input is not used. 103 sot1/pi1 p uart1 data output this function is valid when uart1 data output specification is per- mitted. can be used as a port when uart1 data output specifica- tion is prohibited. 102 sck1/pi2 p uart1 clock input/output this function is valid when uart1 clock output specification is per- mitted. can be used as a port when uart1 clock output specifi- cation is prohibited. 101 sin2/pi3 p uart2 data input this input is always used when uart2 activates input, so output by ports should be stopped except when carried out intentionally. can be used as a port when uart2 data input is not used. 100 sot2/pi4 p uart2 data output this function is valid when uart2 data output specification is per- mitted. can be used as a port when uart2 data output specifica- tion is prohibited. 99 sck2/pi5 p uart2 clock input/output this function is valid when uart2 clock output specification is per- mitted. can be used as a port when uart2 clock output specifi- cation is prohibited. 98 sin3/pj0 p uart3 data input this input is always used when uart3 activates input, so output by ports should be stopped except when carried out intentionally. can be used as a port when uart3 data input is not used. 97 sot3/pj1 p uart3 data output this function is valid when uart3 data output specification is per- mitted. can be used as a port when uart3 data output specifica- tion is prohibited.
mb91133/mb91f133 15 (continued) pin no. pin name circuit type function 96 sck3/pj2 p uart3 clock input/output this function is valid when uart3 clock output specification is per- mitted. can be used as a port when uart3 clock output specifi- cation is prohibited. 95 sin4/pj3 p uart4 data input this input is always used when uart4 activates input, so output by ports should be stopped except when carried out intentionally. can be used as a port when uart4 data input is not used. 94 sot4/pj4 p uart4 data output this function is valid when uart4 data output specification is per- mitted. can be used as a port when uart4 data output specifica- tion is prohibited. 93 sck4/pj5 p uart4 clock input/output this function is valid when uart4 clock output specification is per- mitted. can be used as a port when uart4 clock output specifi- cation is prohibited. 118 119 120 121 122 123 124 125 an0/pk0 an1/pk1 an2/pk2 an3/pk3 an4/pk4 an5/pk5 an6/pk6 cmp/an7/pk7 n a / d converter analog input this is valid when the aick register specification is analog input. [ cmp ] level comparator input can be used as ports when a/d converter analog input is not used. 126 dreq0/pl0 f dma external transfer request input this input is always used if selected as the transfer factor for the dma controller, so output by ports should be stopped except when carried out intentionally. can be used as a port when dma exter- nal transfer request input is not used. 127 dack0/pl1 f dma external transfer request reception output this function is valid when external transfer request reception out- put specification of the dma controller is permitted. can be used as a port when transfer request reception output specification of the dma controller is prohibited. 128 deop0/pl2 f dma external transfer termination output this function is valid when external transfer termination output specification of the dma controller is permitted. 129 dreq1/pl3 f dma external transfer request input this input is always used if selected as the transfer factor for the dma controller, so output by ports should be stopped except when carried out intentionally. can be used as a port when dma exter- nal transfer request input is not used.
mb91133/mb91f133 16 (continued) note : in most of the above pins, the input/output of the i/o ports and resources are multiplexed, such as xxxx/pxx. if the output from ports and resources of those pins compete with each other, the resource is given priority. pin no. pin name circuit type function 130 dack1/pl4 f dma external transfer request reception output this function is valid when external transfer request reception out- put specification of the dma controller is permitted. can be used as a port when transfer request reception output specification of the dma controller is prohibited. 131 deop1/pl5 f dma external transfer termination output this function is valid when external transfer termination output specification of the dma controller is permitted. 132 dreq2/pl6 f dma external transfer request input this input is always used if selected as the transfer factor for the dma controller, so output by ports should be stopped except when carried out intentionally. can be used as a port when dma exter- nal transfer request input is not used. 133 dack2/pl7 f dma external transfer request reception output this function is valid when external transfer request reception out- put specification of the dma controller is permitted. can be used as a port when transfer request reception output specification of the dma controller is prohibited. 134 rst b external reset input 136 137 x0a x1a k oscillation pin for low-speed clock (32 khz) 139 140 x0 x1 a oscillation pin for high-speed clock (16.5 mhz) 142 143 144 md0 md1 md2 g mode pins basic mcu operation mode is set by these pins. they should be directly connected to v cc or v ss for use. 112 davs ? ground pin of d/a converter (connected to analog ground) 113 davc ? power pin of d / a converter 114 av cc ? power pin for a / d converter 115 avrh ? reference voltage pin for a / d converter (high electric poten- tial side) when this pin is turned on/off, avrh or more electric potential must be supplied to v cc . 116 avrl ? reference voltage pin for a / d converter (low electric potential side) 117 av ss ? ground pin for a / d converter (connected to analog ground) 27, 108 v cc 5 ? 5 v power of digital circuit power must be connected to all v cc 5 pins for use. 44, 92 138 v cc 3 ? 3 v power of digital circuit power must be connected to all v cc 3 pins for use. 9, 26, 52, 91, 135, 141 v ss ? ground level of digital circuit
mb91133/mb91f133 17 n input/output circuit types (continued) type circuit remarks a ? high-speed oscillation circuit (16.5 mhz) oscillation feedback resistance = approximately 1 m w 3 v cmos level input b ? with pull up resistance cmos level input pull-up resistance value = approximately 25 k w (typ.) c ? cmos level input/output pin cmos level output cmos level input (with standby control) i ol = 4 ma f ? cmos hysteresis input/output pin cmos level output cmos hysteresis input (with standby control) i ol = 4 ma x1 x0 xout standby control signal digital input pout nout cmos input standby control r pout nout hysteresis input standby control r
mb91133/mb91f133 18 (continued) type circuit remarks g ? cmos level input pin cmos level input (without standby control) i ol = 4 ma h ? cmos hysteresis input/output pin with pull- up control cmos level output cmos hysteresis input (without standby control) pull-up resistance value = approximately 50 k w (typ.) i ol = 4 ma k ? clock oscillation circuit (32 khz) oscillation feedback resistance = approximately 4.5 m w /3 v 3 v cmos level input n ? analog/cmos level input/output pin cmos level output cmos level input (with standby control) analog input (analog input is valid when bit dealt by aic is 1.) i ol = 4 ma r digital input r r pout pull-up control hysteresis input nout x1a x0a xout standby control signal pout cmos input standby control analog input nout r
mb91133/mb91f133 19 (continued) type circuit remarks o ? cmos hysteresis input/output pin with pull-up control cmos level output cmos hysteresis input (with standby control) pull-up resistance value = approximately 50 k w (typ.) i ol = 4 ma p ? cmos hysteresis input/output pin with pull-up control cmos level output (with open-drain control) cmos hysteresis input (with standby control) pull-up resistance value = approximately 50 k w (typ) i ol = 4 ma pout pull-up control hysteresis input standby control nout r r nout pull-up control open-drain control hysteresis input standby control r r
mb91133/mb91f133 20 n handling devices 1. points to note on handling devices (1) latch-up prevention latch-up may occur by cmos ic if a voltage in excess of v cc 5 or lower than v ss is applied to the input/output pins, or if the voltage exceeds the rating between v cc 5 and v ss . if latch-up occurs, the electrical current increases significantly and may destroy certain components due to excessive heat, so great care must be taken to ensure that the maximum rating is not exceeded during use. (2) handling pins ? handling unused pins input pins that are not used should be pulled up or down as they may cause erroneous operations if left open. ? handling n.c. pins n.c. pins must be opened for use. ? handling output pins excessive electric current may flow if the output pin is shorted by the power source or other output pins, or connected to large loads. if such status is prolonged, the device is liable to be damaged, so great care must be taken to ensure that the usage volume does not exceed the maximum rating. ? mode pins (md0 to md2) those pins must be directly connected to v cc 5 or v ss for use. pattern lengths between v cc 5 or v ss and each mode pin on the printed-circuit board should be arranged to be as short as possible to prevent the test mode from being erroneously turned on due to noise, and they should be connected with low impedance. ? power pins when there are a number of v cc 5/v cc 3/v ss , those whose electrical potential must be the same within the device are connected to prevent erroneous operation such as latch-up for device design purposes, but those must be externally connected to a power source and earthed to follow the general output current standard and prevent erroneous operation of strobe signals due to increased ground level and reduction in unnecessary radiation. care must also be taken to ensure that they are connected to the v cc 5/v ss or v cc 3/v ss of this device at the lowest possible impedance from the source of the electrical current supply. furthermore, it is recommended that a ceramic capacitor of around 0.1 m f be used to connect the v cc 5 and v ss , or v cc 3 and v ss near the device as a bypass capacitor. ? crystal oscillation circuits noise near the x0, x1, x0a or x1a pins can cause erroneous operation. the printed-circuit board must be designed so that the x0, x1, x0a and x1a pins, crystal oscillator (or ceramic oscillator) and bypass capacitor to the ground can be arranged as close as possible. also, a printed-circuit board with grounded artwork enclosing the x0, x1, x0a and x1a pins is strongly recommended to ensure stable operation.
mb91133/mb91f133 21 (3) points to note on usage ? external reset input l level should be input to the rst pin, which is required for at least five machine cycles to ensure that the internal status is reset. ? oscillation pin oscillation pin is 3 v cmos input level. ? external clock use with an external clock is prohibited. a crystal (or ceramic) oscillator should be used. ? analog power the av cc should always be used at the same electric potential as v cc 5. if the v cc 5 is larger than the av cc , electricity may flow through pins an 0 to an 7. ? points to note for using level comparator when the level comparator is used, a reference current (ir) flows even though it is stopped. the stop mode must be turned on after prohibiting action of the level comparator. 2. points to note on turning on power ? rst pin handling the rst pin must be started from l level when the power is turned on, and when the power is adjusted to the v dd level, it should be changed to the h level after being left on for at least 5 cycles of the internal operation clock. ? original oscillation input the clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on. ? power on reset power on reset must be executed if power is turned on, but the power voltage falls below the guaranteed operating temperature and power is turned on again. ? order for turning on power power should be turned on in the following order. v cc 3 ? v cc 5 ? av cc ? avrh the opposite order should be used when turning off.
mb91133/mb91f133 22 n block diagram * : int23 to int16 share pins with a23 to a16 * : int15 shares pins with atg * : int14 shares pins with deop2 * : int13 to int8 share pins with trg5 to trg0 * : int7 to int4 share pins with ain0, bin0, ain1 and bin1 the total number of above pins is 133. the remainder (144 - 133 = 11 pins) are v cc 5 , v cc 3 and v ss . fr30 cpu ram 6 kbyte dmac 8 ch dreq0 todreq 2 dack0 todack 2 deop0 to deop2 resource bus controller bus converter ram 2 kbyte rom 254 kbyte external bus controller a23 to a00 d31 to d16 rd rdy brq bgrnt clk wr1, wr0 interrupt controller clock generator up/down counter 2 ch 24 ch external interrupt 10 bit 8 input a/d converter level comparator x0, x1, x0a, x1a rst md0 to md2 47 9 8 ain0, 1 bin0, 1 zin0, 1 int0 to int23 ( * ) 6 24 an0 to an7 avrh, avrl av cc , av ss cmp (an7) 12 15 5 6 6 sin0 to sin4 sot0 to sot4 sck0 to sck4 uart 5 ch reload timer 5 ch 8 bit 3 output d/a converter da0 toda2 ppg0 to ppg5 trg0 to trg5 in0 to in3 frck davc, davs 4 multi-function timer 16 bit ppg 6 ch 16 bit icu 4 ch 16 bit frt 16 bit ocu 8 ch waveform generator rto0 (u) rto1 (x) rto2 (v) rto3 (y) rto4 (w) rto5 (z) rto6 rto7 dtti
mb91133/mb91f133 23 n cpu 1. memory space the fr series has 4 gbytes (2 32 addresses) of logic address space which the cpu accesses linearly. ? memory map * : it is impossible to access the external area on single-chip mode. when accessing the external area, select the internal rom external bus mode. i/o i/o i/o i/o i/o external rom external bus mode internal rom external bus mode single-chip mode i/o access is prohibited access is prohibited access is prohibited built-in ram 6 kb built-in ram 6 kb built-in ram 6 kb access is prohibited access is prohibited access is prohibited external area external area external area built-in ram 2kb built-in ram 2kb built-in rom 254kb built-in rom 254kb access is prohibited access is prohibited 0000 0000 h 0000 0400 h 0000 0800 h 0000 1000 h 0000 2800 h 0001 0000 h ffff ffff h 010 0000 h 000c 0000 h 000c 0800 h 0001 0000 h refer to "i/o map" direct madressing area ffff ffff h
mb91133/mb91f133 24 2. registers there are two types of multi-purpose registers in the fr family. one is a dedicated purpose register that exists within the cpu and the other is a multi-purpose register that exists in the memory. ? dedicated registers ? program status (ps) ps is the register that holds the program status and is classified into three categories, namely, condition code register (ccr) , system condition code register (scr) and interruption level master register (ilm) . program counter (pc) : 32-bit length; indicates instruction storage position. program status (ps) : 32-bit length; stores register pointers and condition codes. table base register (tbr) : holds the starting address of the vector table to be used for exception, interruption and trapping (eit) . return pointer (rp) : holds the address to return to from the sub-routine. system stuck pointer (ssp) : indicates the system stuck position. user stuck pointer (usp) : indicates the users stuck position. multiplication and division results resister (mdh/mdl) : 32-bit length; act as registers for multiplication and division. pc ps tbr rp ssp usp mdh mdl xxxx xxxx h initial values xxxx xxxx h xxxx xxxx h xxxx xxxx h xxxx xxxx h (undecided) (undecided) (undecided) (undecided) (undecided) 0000 0000 h 000f fc00 h program counter return pointer user stuck pointer program status multiplication and division results resister system stuck pointer table base register 32 bit ps ilm4 ilm3 ilm2 ilm scr ccr ilm1 ilm0 d1 d0 t s i n z v c 0 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 31 ????
mb91133/mb91f133 25 ? condition code register (ccr) ? system condition code register (scr) ? interruption level mask register ( ilm ) s flag : specifies the stuck pointer to be used as r15. i flag : controls permission and prohibition of user interruption requests. n flag : indicates codes when computation results are defined as integers that are expressed in comple- ments of 2. z flag : indicates whether or not a result of the computation is 0 . v flag : operands used for computation are defined as integers expressed in complements of 2, and indi- cate whether or not an overflow is generated as a result of the computation. c flag : indicates whether carrying or borrowing is generated from the highest bit as a result of the compu- tation. t flag : specifies whether or not the step trace trap will be valid. ilm4 to ilm0 : holds the interruption level mask values, and those values that are held by the ilm are used for the level mask. interruption requests can be accepted only when the interruption levels handled within the interruption requests to be input into the cpu are stronger than the levels shown by the ilm. ilm4 ilm3 ilm2 ilm1 ilm0 interruption level strength 00000 0 strong 01000 15 11111 31 weak
mb91133/mb91f133 26 n multi-purpose registers the multi-purpose registers are cpu registers r0 to r15 which are used as accumulators for various compu- tations and memory access pointers (fields that indicate the address) . special purposes are assumed for the following 3 of the 16 registers. thus, some instructions are emphasized. r13 : virtual accumulator (ac) r14 : frame pointer (fp) r15 : stack pointer (sp) initial values for r0 to r14 on resetting are unspecified. the initial value of r15 will be 0000 0000 h (ssp value) . ? register bank configuration r0 r1 r12 r13 r14 r15 ac (accumulator) 32-bit fp (frame pointer) sp (stack pointer) xxxx xxxx h initial value xxxx xxxx h 0000 0000 h
mb91133/mb91f133 27 n mode setting 1. pins ? mode pins and set mode 2. register mode register (modr) and set mode ? bus mode set bit and its functions mode pins mode name reset vector access areas external data bus width bus modes md2 md1 md0 0 0 0 external vector mode 0 external 8-bit external rom external bus mode 0 0 1 external vector mode 1 external 16-bit 010 ??? setting is prohibited 0 1 1 internal vector mode internal (mode register) single chip mode 1 ?? ? ? ? usage is prohibited m1 m0 functions remarks 0 0 single chip mode 0 1 internal rom external bus mode 1 0 external rom external bus mode 11 ? setting is prohibited address initial value access 0000 07ff h xxxx xxxx b w m1 m0 bus mode set bit ****** w : write only x : undecided * : 0 should always be written for bits other than m1 and m0.
mb91133/mb91f133 28 n i/o map (continued) address register block + 0 + 1 + 2 + 3 000000 h pdr3 (r/w) pdr2 (r/w) ? port data register xxxxxxxx xxxxxxxx 000004 h ? pdr6 (r/w) pdr5 (r/w) pdr4 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx 000008 h ??? pdr8 (r/w) - xxxxxxx 00000c h ? 000010 h pdrf (r/w) pdre (r/w) pdrd (r/w) pdrc (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000014 h pdrj (r/w) pdri (r/w) pdrh (r/w) pdrg (r/w) - - xxxxxx - - xxxxxx - - - - - xxx - - xxxxxx 000018 h lvlc (r/w) ? pdrl (r/w) pdrk (r/w) level comparator xxxx 0 0 0 0 xxxxxxxx xxxxxxxx 00001c h ssr0 (r/w) sidr0/sodr0 (r/w) scr0 (r/w) smr0 (r/w) uart0 0 0 0 0 1 - 0 0 xxxxxxxx 0 0 0 0 0 1 0 0 0 0 0 0 0 - 0 0 000020 h ssr1 (r/w) sidr1/sodr1 (r/w) scr1 (r/w) smr1 (r/w) uart1 0 0 0 0 1 - 0 0 xxxxxxxx 0 0 0 0 0 1 0 0 0 0 0 0 0 - 0 0 000024 h ssr2 (r/w) sidr2/sodr2 (r/w) scr2 (r/w) smr2 (r/w) uart2 0 0 0 0 1 - 0 0 xxxxxxxx 0 0 0 0 0 1 0 0 0 0 0 0 0 - 0 0 000028 h tmrlr (w) tmr (r) reload timer 0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00002c h ? tmcsr (r/w) - - - - 0 0 0 0 0 0 0 0 0 0 0 0 000030 h tmrlr (w) tmr (r) reload timer 1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000034 h ? tmcsr (r/w) - - - - 0 0 0 0 0 0 0 0 0 0 0 0 000038 h adcr (r/w) adcs1 (r/w) adcs0 (r/w) a/d converter (sequential type) 0 0 1 0 1 - xx xxxxxxxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00003c h tmrlr (w) tmr (r) reload timer 2 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000040 h ? tmcsr (r/w) - - - - 0 0 0 0 0 0 0 0 0 0 0 0
mb91133/mb91f133 29 (continued) address register block + 0 + 1 + 2 + 3 000044 h ipcp1 (r) ipcp0 (r) 16-bit icu xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000048 h ipcp3 (r) ipcp2 (r) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00004c h ? ics23 (r/w) ? ics01 (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000050 h ? reserved 000054 h occp1 (r/w) occp0 (r/w) 16-bit ocu xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000058 h occp3 (r/w) occp2 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00005c h occp5 (r/w) occp4 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000060 h occp7 (r/w) occp6 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000064 h ocs32 (r/w) ocs10 (r/w) xxx 0 0 0 0 0 0 0 0 0 xx 0 0 xxx 0 0 0 0 0 0 0 0 0 xx 0 0 000068 h ocs76 (r/w) ocs54 (r/w) xxx 0 0 0 0 0 0 0 0 0 xx 0 0 xxx 0 0 0 0 0 0 0 0 0 xx 0 0 00006c h tcdt (r/w) tccs (r/w) 16-bit free-run timer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - - - - 0 0 0 0 0 0 0 0 000070 h ssr3 (r/w) sidr3/sodr3 (r/w) scr3 (r/w) smr3 (r/w) uart3 0 0 0 0 1 0 0 0 xxxxxxxx 0 0 0 0 0 1 0 0 0 0 0 0 0 - 0 0 000074 h ssr4 (r/w) sidr4/sodr4 (r/w) scr4 (r/w) smr4 (r/w) uart4 0 0 0 0 1 0 0 0 xxxxxxxx 0 0 0 0 0 1 0 0 0 0 0 0 0 - 0 0 000078 h cdcr1 (r/w) ? cdcr0 (r/w) ? communication pre-scalar 0 - - - 0 0 0 0 0 - - - 0 0 0 0 00007c h cdcr3 (r/w) ? cdcr2 (r/w) ? 0 - - - 0 0 0 0 0 - - - 0 0 0 0 000080 h ? cdcr4 (r/w) ? 0 - - - 0 0 0 0
mb91133/mb91f133 30 (continued) address register block + 0 + 1 + 2 + 3 000084 h rcr1 (w) rcr0 (w) udcr1 (r) udcr0 (r) 8-/16-bit u/d counter 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000088 h ccrh0 (r/w) ccrl0 (r/w) ? csr0 (r/w) 0 0 0 0 0 0 0 0 - 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00008c h ccrh1 (r/w) ccrl1 (r/w) ? csr1 (r/w) - 0 0 0 0 0 0 0 - 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 000090 h ? reserved 000094 h eirr0 (r/w) enir0 (r/w) eirr1 (r/w) enir1 (r/w) ext int 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000098 h elvr0 (r/w) elvr1 (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00009c h eirr2 (r/w) enir2 (r/w) ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000a0 h elvr2 (r/w) ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000a4 h ? dacr2 (r/w) dacr1 (r/w) dacr0 (r/w) d/a converter - - - - - - - 0- - - - - - - 0- - - - - - - 0 0000a8 h ? dadr2 (r/w) dadr1 (r/w) dadr0 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx 0000ac h dtcr1 (r/w) tmrr1 (r/w) dtcr0 (r/w) tmrr0 (r/w) waveform generator 0 0 0 0 0 0 0 0 xxxxxxxx 0 0 0 0 0 0 0 0 xxxxxxxx 0000b0 h ? sigcr (r/w) dtcr2 (r/w) tmrr2 (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 xxxxxxxx 0000b4 h to 0000bc h ? reserved 0000c0 h ? pcre (r/w) pcrd (r/w) pcrc (r/w) pull-up control - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000c4 h pcrj (r/w) pcri (r/w) pcrh (r/w) ? - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - - - - 0 0 0 0000c8 h ocrj (r/w) ocri (r/w) ocrh (r/w) ? open-drain control - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - - - - 0 0 0 0000cc h ??? aick (r/w) analog input control 0 0 0 0 0 0 0 0
mb91133/mb91f133 31 (continued) address register block + 0 + 1 + 2 + 3 0000d0 h ddrf (r/w) ddre (r/w) ddrd (r/w) ddrc (r/w) data direction register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000d4 h ddrj (r/w) ddri (r/w) ddrh (r/w) ddrg (r/w) - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - - - - 0 0 0 - - 0 0 0 0 0 0 0000d8 h ?? ddrl (r/w) ddrk (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000dc h gcn1 (r/w) ? gcn2 (r/w) ppg ctl 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0000e0 h ptmr0 (r) pcsr0 (w) ppg0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xxxxxxxx xxxxxxxx 0000e4 h pdut0 (w) pcnh0 (r/w) pcnl0 (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0000e8 h ptmr1 (r) pcsr1 (w) ppg1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xxxxxxxx xxxxxxxx 0000ec h pdut1 (w) pcnh1 (r/w) pcnl1 (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0000f0 h ptmr2 (r) pcsr2 (w) ppg2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xxxxxxxx xxxxxxxx 0000f4 h pdut2 (w) pcnh2 (r/w) pcnl2 (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0000f8 h ptmr3 (r) pcsr3 (w) ppg3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xxxxxxxx xxxxxxxx 0000fc h pdut3 (w) pcnh3 (r/w) pcnl3 (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 000100 h ptmr4 (r) pcsr4 (w) ppg4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xxxxxxxx xxxxxxxx 000104 h pdut4 (w) pcnh4 (r/w) pcnl4 (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 000108 h ptmr5 (r) pcsr5 (w) ppg5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 xxxxxxxx xxxxxxxx 00010c h pdut5 (w) pcnh5 (r/w) pcnl5 (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0
mb91133/mb91f133 32 (continued) address register block + 0 + 1 + 2 + 3 000110 h tmrlr (w) tmr (r) reload timer 3 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000114 h ? tmcsr (r/w) - - - - 0 0 0 0 0 0 0 0 0 0 0 0 000118 h tmrlr (w) tmr (r) reload timer 4 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00011c h ? tmcsr (r/w) - - - - 0 0 0 0 0 0 0 0 0 0 0 0 000120 h to 0001fc h ? reserved 000200 h dpdp (r/w) dmac - - - - - - - -- - - - - - - -- - - - - - - -- 0 0 0 0 0 0 0 000204 h dacsr (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000208 h datcr (r/w) xxxxxxxx xxxx0 0 0 0 xxxx0 0 0 0 xxxx0 0 0 0 00020c h ? 000210 h to 0003ec h ? reserved 0003f0 h bsd0 (w) bit search module xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003e4 h bsd1 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc (w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr (r) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h icr00 (r/w) icr01 (r/w) icr02 (r/w) icr03 (r/w) interrupt control unit - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000404 h icr04 (r/w) icr05 (r/w) icr06 (r/w) icr07 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000408 h icr08 (r/w) icr09 (r/w) icr10 (r/w) icr11 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1
mb91133/mb91f133 33 (continued) address register block + 0 + 1 + 2 + 3 00040c h icr12 (r/w) icr13 (r/w) icr14 (r/w) icr15 (r/w) interrupt control unit - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000410 h icr16 (r/w) icr17 (r/w) icr18 (r/w) icr19 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000414 h icr20 (r/w) icr21 (r/w) icr22 (r/w) icr23 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000418 h icr24 (r/w) icr25 (r/w) icr26 (r/w) icr27 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 00041c h icr28 (r/w) icr29 (r/w) icr30 (r/w) icr31 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000420 h icr32 (r/w) icr33 (r/w) icr34 (r/w) icr35 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000424 h icr36 (r/w) icr37 (r/w) icr38 (r/w) icr39 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000428 h icr40 (r/w) icr41 (r/w) icr42 (r/w) icr43 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 00042c h icr44 (r/w) icr45 (r/w) icr46 (r/w) icr47 (r/w) - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 000430 h dicr (r/w) hrcl (r/w) ? delay int - - - - - - - 0- - - 1 1 1 1 1 000434 h to 00047c h ? reserved 000480 h rsrr/wtcr (r/w) stcr (r/w) pdrr (r/w) ctbr (w) clock control unit 1 xxxx - 0 0 0 0 0 1 1 1 - -- - - - 0 0 0 0 xxxxxxxx 000484 h gcr (r/w) wpr (w) ? 1 1 0 0 1 1 - 1 xxxxxxxx 000488 h ct (r/w) ? pll control 0 0 - - 0 - 0 0 00048c h to 0005fc h ? reserved
mb91133/mb91f133 34 (continued) address register block + 0 + 1 + 2 + 3 000600 h ddr3 (w) ddr2 (w) ?? data direction register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000604 h ? ddr6 (w) ddr5 (w) ddr4 (w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000608 h ??? ddr8 (w) - 0 0 0 0 0 0 0 00060c h asr1 (w) amr1 (w) t-unit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000610 h asr2 (w) amr2 (w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000614 h asr3 (w) amr3 (w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000618 h asr4 (w) amr4 (w) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00061c h asr5 (w) amr5 (w) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000620 h amd0 (r/w) amd1 (r/w) amd32 (r/w) amd4 (r/w) - - - 0 0 1 1 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - 0 0 0 0 0 000624 h amd5 (r/w) ? 0 - - 0 0 0 0 0 000628 h epcr0 (w) epcr1 (w) - - - - 1 1 0 0 - 1 - - - - - -- - - - - - - - 1 1 1 1 1 1 1 1 00062c h ? 000630 h ? pcr6 (r/w) ? pull-up control 0 0 0 0 0 0 0 0 000634 h to 0007bc h ? reserved 0007c0 h flcr (r/w) ? flash control 0 0 0 x 0 0 0 0 0007c4 h fwtc (r/w) ? - - - - - 0 0 0 0007c8 h to 0007f8 h ? reserved
mb91133/mb91f133 35 (continued) *1 : do not execute rmw instructions to registers with write-only bits. *2 : do not execute write access to read-only or reserved registers except for particular requests. *3 : data in areas with - or reserved ones are unspecified. *4 : rmw instructions (rmw : read / modify / write) address register block + 0 + 1 + 2 + 3 0007fc h ? ler (w) modr (w) little endian register mode register - - - - - 0 0 0 xxxxxxxx and rj, @ri or rj, @ri eor rj, @ri andh rj, @ri orh rj, @ri eorh rj, @ri andb rj, @ri orb rj, @ri eorb rj, @ri bandl #u4, @ri borl #u4, @ri beorl #u4, @ri bandh #u4, @ri borh #u4, @ri beorh #u4, @ri
mb91133/mb91f133 36 n interruption vector causes of mb91130 interruptions and allocation of interruption vectors and interruption control registers are described in the interruption vector table. (continued) interruption sauce interruption number interruption level *1 offset address *2 of tbr default decimal hexadecimal reset 0 00 ? 3fc h 000ffffc h system reservation 1 01 ? 3f8 h 000ffff8 h system reservation 2 02 ? 3f4 h 000ffff4 h system reservation 3 03 ? 3f0 h 000ffff0 h system reservation 4 04 ? 3ec h 000fffec h system reservation 5 05 ? 3e8 h 000fffe8 h system reservation 6 06 ? 3e4 h 000fffe4 h system reservation 7 07 ? 3e0 h 000fffe0 h system reservation 8 08 ? 3dc h 000fffdc h system reservation 9 09 ? 3d8 h 000fffd8 h system reservation 10 0a ? 3d4 h 000fffd4 h system reservation 11 0b ? 3d0 h 000fffd0 h system reservation 12 0c ? 3cc h 000fffcc h system reservation 13 0d ? 3c8 h 000fffc8 h exceptions to undefined instructions 14 0e ? 3c4 h 000fffc4 h system reservation 15 0f ? 3c0 h 000fffc0 h external interruption 0 16 10 icr00 3bc h 000fffbc h external interruption 1 17 11 icr01 3b8 h 000fffb8 h external interruption 2 18 12 icr02 3b4 h 000fffb4 h external interruption 3 19 13 icr03 3b0 h 000fffb0 h external interruption 4 20 14 icr04 3ac h 000fffac h external interruption 5 21 15 icr05 3a8 h 000fffa8 h external interruption 6 22 16 icr06 3a4 h 000fffa4 h external interruption 7 23 17 icr07 3a0 h 000fffa0 h external interruption 8 to 15 24 18 icr08 39c h 000fff9c h external interruption 16 to 23 25 19 icr09 398 h 000fff98 h uart0 (reception completion) 26 1a icr10 394 h 000fff94 h uart1 (reception completion) 27 1b icr11 390 h 000fff90 h uart2 (reception completion) 28 1c icr12 38c h 000fff8c h uart3 (reception completion) 29 1d icr13 388 h 000fff88 h uart4 (reception completion) 30 1e icr14 384 h 000fff84 h
mb91133/mb91f133 37 (continued) interruption sauce interruption number interruption level *1 offset address *2 of tbr default decimal hexadecimal uart0 (transmission completion) 31 1f icr15 380 h 000fff80 h uart1 (transmission completion) 32 20 icr16 37c h 000fff7c h uart2 (transmission completion) 33 21 icr17 378 h 000fff78 h uart3 (transmission completion) 34 22 icr18 374 h 000fff74 h uart4 (transmission completion) 35 23 icr19 370 h 000fff70 h dmac (end, error) 36 24 icr20 36c h 000fff6c h reload timer 0 37 25 icr21 368 h 000fff68 h reload timer 1 38 26 icr22 364 h 000fff64 h reload timer 2 39 27 icr23 360 h 000fff60 h reload timer 3 40 28 icr24 35c h 000fff5c h reload timer 4 41 29 icr25 358 h 000fff58 h a/d (sequential type) 42 2a icr26 354 h 000fff54 h ppg0 43 2b icr27 350 h 000fff50 h ppg1 44 2c icr28 34c h 000fff4c h ppg2 45 2d icr29 348 h 000fff48 h ppg3 46 2e icr30 344 h 000fff44 h ppg4/5 47 2f icr31 340 h 000fff40 h waveform generator 48 30 icr32 33c h 000fff3c h u/d counter 0 (compare/ underflow-overflow, up/down invert) 49 31 icr33 338 h 000fff38 h u/d counter 1 (compare/ underflow-overflow, up/down invert) 50 32 icr34 334 h 000fff34 h icu0 (load) 51 33 icr35 330 h 000fff30 h icu1 (load) 52 34 icr36 32c h 000fff2c h icu2 (load) 53 35 icr37 328 h 000fff28 h icu3 (load) 54 36 icr38 324 h 000fff24 h ocu0 (matched) 55 37 icr39 320 h 000fff20 h ocu1 (matched) 56 38 icr40 31c h 000fff1c h ocu2 (matched) 57 39 icr41 318 h 000fff18 h ocu3 (matched) 58 3a icr42 314 h 000fff14 ocu4/5 (matched) 59 3b icr43 310 h 000fff10 h ocu6/7 (matched) 60 3c icr44 30c h 000fff0c h level comparator 61 3d icr45 308 h 000fff08 h 16-bit freerun timer 62 3e icr46 304 h 000fff04 h delay interruption factor bit 63 3f icr47 300 h 000fff00 h
mb91133/mb91f133 38 (continued) *1 : icr sets the interruption level for each interruption request using the register built into the interruption controller. icr is prepared in accordance with each interruption request. *2 : tbr is the register that indicates the starting address of the vector table for eit. addresses with added offset values that are specified per tbr and eit factor will be the vector addresses. *3 : 0x40, 0x41 interruptions for system codes are used in the event that realos/fr is used. interruption sauce interruption number interruption level *1 offset address *2 of tbr default decimal hexadecimal system reservation (used under realos *3 ) 64 40 ? 2fc h 000ffefc h system reservation (used under realos *3 ) 65 41 ? 2f8 h 000ffef8 h used under int instruction 66 42 ? 2f4 h 000ffef4 h used under int instruction 67 43 ? 2f0 h 000ffef0 h used under int instruction 68 44 ? 2ec h 000ffeec h used under int instruction 69 45 ? 2e8 h 000ffee8 h used under int instruction 70 46 ? 2e4 h 000ffee4 h used under int instruction 71 47 ? 2e0 h 000ffee0 h used under int instruction 72 48 ? 2dc h 000ffedc h used under int instruction 73 49 ? 2d8 h 000ffed8 h used under int instruction 74 4a ? 2d4 h 000ffed4 h used under int instruction 75 4b ? 2d0 h 000ffed0 h used under int instruction 76 4c ? 2cc h 000ffecc h used under int instruction 77 4d ? 2c8 h 000ffec8 h used under int instruction 78 4e ? 2c4 h 000ffec4 h used under int instruction 79 4f ? 2c0 h 000ffec0 h used under int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h
mb91133/mb91f133 39 n peripheral resources 1. bus interface the bus interface controls the interface with external memory and external i/o. ? bus interface characteristics ? 24-bit (16 mb) address output ? 16/8-bit bus width can be set. ? insertion of programmable automatic memory wait (maximum of 7 cycles) ? supports little endian mode ? unused addresses / data pins can be used as i/o ports. ? clock doubled should be used if the external bus exceeds 25 mhz. bus speed is 1/2 of the cpu speed. ? areas a total of six types of chip selection areas are prepared for the bus interface. the position of each area can be randomly arranged per 64 kb at least using area selection registers (asr1 to asr 5) and area mask registers (amr1 to amr 5) in an area of 4 gb. the area 0 is allocated to space outside the area specified by asr1 to asr5. external areas other than 00010000 h to 0005ffff h are deemed area 0 on resetting. there is no chip selection output pin so no setting is required. setting it has no effect on usage. figure 4.1-1 shows an example in which areas 1 to 5 are arranged from 00100000 h to 0014ffff h in 64 kb units. also, figure 4.1-2 shows an example in which area 1 is arranged as 00000000 h to 0007ffff h in 512 kb and areas 2 to 5 are arranged as 00100000 h to 004fffff h in 1-mb units. 00000000 h 00000000 h 00080000 h 000fffff h 001fffff h 002fffff h 003fffff h 004fffff h 00080000 h 000fffff h 0010ffff h 0011ffff h 0012ffff h 0013ffff h 0014ffff h cs0 (1 mbyte) cs1 (512 k) cs0 (512 k) cs2 (1 mbyte) cs3 (1 mbyte) cs4 (1 mbyte) cs5 (1 mbyte) cs0 cs0 cs1 (64 kbyte) cs2 (64 kbyte) cs3 (64 kbyte) cs4 (64 kbyte) cs5 (64 kbyte) figure 4.1-1 area arrangement example 1 figure 4.1-2 area arrangement example 2
mb91133/mb91f133 40 ? block diagram write buffer read buffer address buffer switch switch a - out m u x external data bus asr amr registers & control shifter compa- rator inpage external pin control area + 1 or + 2 data block address block external address bus cs0 - cs5 controls all blocks rd wr0. wr1 brq bgrnt rdy address bus data b u s
mb91133/mb91f133 41 ? register list 0000060c h 0000060e h 00000610 h 00000612 h 00000614 h 00000616 h 00000618 h 0000061a h 0000061c h 0000061e h 00000620 h 00000622 h 00000624 h 00000626 h 0000062c h 0000062e h 00000688 h 000007fe h asr1 area select register 1 area mask register 1 area select register 2 area mask register 2 area select register 3 area mask register 3 area select register 4 area mask register 4 area select register 5 area mask register 5 area mode register 0 / area mode register 1 area mode register 32 / area mode register 4 area mode register 5 refresh control register dram control register 4 dram control register 4 external pin control register little endian register / mode register amr1 asr2 amr2 asr3 amr3 asr4 amr4 asr5 amr5 rfcr dmcr5 dmcr4 epcr0 epcr1 ler modr amd5 ? amd0 amd1 amd32 amd4 15 address 87 0 note : functional pins have not been prepared in the shaded area for mb91133/mb91f133, so these registers should not be accessed.
mb91133/mb91f133 42 2. i/o port mb91133/mb91f133 can be used as an i/o port when the setting for resources dealing with each pin does not use the pin for input/output. as regards the read value of the port (pdr) , the pin level is read out when input is set for the port. if output is set, the data register value is read out. this is the same for reading under read modify write. if the input setting is changed to output setting, output data should be set first. if read modify write instructions (i.e. bit set) are used in this case, the data that is read out is the input data from the pin and is not the latch value of the data register, so care must be taken. ? basic i/o port block diagram ? i/o port register the i/o port consists of the port data register (pdr) and port direction register (ddr) . ? in case of input mode (ddr = 0) when pdr reads : level of external pins handled is read out. when pdr writes : set value is written in pdr. ? in case of output mode (ddr = 1) when pdr reads : pdr values are read out. when pdr writes : pdr values are output to the external pin handled. ? switching control for resources and ports of the analog pin (a/d) ? resources and ports of the analog pin (a/d) are switched using the analog input control register on port k (aick) . this controls whether port k is used as an analog or general-purpose port. 0 : general-purpose port 1 : analog input (a/d) data bus pdr read resource input resource output resource output permission 0 1 0 1 pin pdr ddr pdr : port data register ddr : data direction register
mb91133/mb91f133 43 ? block diagram of input/output port (with pull-up resistance) ? pull-up resistance control register (pcr) r/w turns pull-up resistance on/off. 0 : pull-up resistance turned off 1 : pull-up resistance turned on notes : the pull-up resistance control register setting is handled as a priority in stop mode (hiz = 1) as well. use of the pull-up resistance control function is prohibited when the pin concerned is used as the external bus pin. 1 should not be written in this register. data bus pdr read 0 1 0 1 pin pdr ddr pcr pdr : port data register ddr : data direction register pcr : pull-up control register resource input pull up resistance (approximately 50 k w ) resource output resource output permission
mb91133/mb91f133 44 ? block diagram of input / output port (open-drain output function with pull-up resistance) ? pull-up resistance control register (pcr) r/w controls pull up resistance on/off. 0 : without pull-up resistance 1 : with pull-up resistance ? open-drain control register (odcr) r/w controls open-drain in output mode. 0 : standard output port in output mode 1 : open-drain output port in output mode notes : this has no meaning in input mode (output hi-z) . input/output mode is decided by the direction register (ddr) . pull-up resistance control register setting is handled as the priority in stop mode (hiz = 1) as well. use of both the pull-up resistance control function and open-drain control function are prohibited when the pin concerned is used as an external bus pin. 1 should not be written in both registers. data bus pdr read 0 1 0 1 pin pdr ddr odcr pcr pdr ddr odcr pcr : port data register : data direction register : opendrain control register : pull-up control register resource input resource output resource output permission
mb91133/mb91f133 45 ? port data register (pdr) pdr2 to l are input/output data registers of the i/o port. input/output control is carried out by ddr2 to l that are handled. pdr2 initial value access address : 000001 h xxxxxxxx b r/w pdr3 initial value access address : 000000 h xxxxxxxx b r/w pdr4 initial value access address : 000007 h xxxxxxxx b r/w pdr5 initial value access address : 000006 h xxxxxxxx b r/w pdr6 initial value access address : 000005 h xxxxxxxx b r/w pdr8 initial value access address : 00000b h - xxxxxxx b r/w pdrc initial value access address : 000013 h xxxxxxxx b r/w pdrd initial value access address : 000012 h xxxxxxxx b r/w pdre initial value access address : 000011 h xxxxxxxx b r/w pdrf initial value access address : 000010 h xxxxxxxx b r/w pdrg initial value access address : 000017 h - - xxxxxx b r/w pdrh initial value access address : 000016 h - - - - - xxx b r/w pdri initial value access address : 000015 h - - xxxxxx b r/w pdrj initial value access address : 000014 h - - xxxxxx b r/w pdrk initial value access address : 00001b h xxxxxxxx b r/w pdrl initial value access address : 00001a h xxxxxxxx b r/w 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 7654 321 0 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 p86 ? p85 p84 p83 p82 p81 p80 7654 321 0 pc6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 7654 321 0 pd6 pd7 pd5 pd4 pd3 pd2 pd1 pd0 7654 321 0 pe6 pe7 pe5 pe4 pe3 pe2 pe1 pe0 7654 321 0 pf6 pf7 pf5 pf4 pf3 pf2 pf1 pf0 7654 321 0 ? ? pg5 pg4 pg3 pg2 pg1 pg0 7654 321 0 ? ???? ph2 ph1 ph0 7654 321 0 ? ? pi5 pi4 pi3 pi2 pi1 pi0 7654 321 0 ? ? pj5 pj4 pj3 pj2 pj1 pj0 7654 321 0 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0 7654 321 0 pl6 pl7 pl5 pl4 pl3 pl2 pl1 pl0
mb91133/mb91f133 46 ? data direction register (ddr) ddr0 to l control input/output direction of the i/o ports handled per bit. ddr = 0 : port input ddr = 1 : port output 0 must be written into the empty bit. ddr2 initial value access address : 000601 h 00000000 b w ddr3 initial value access address : 000600 h 00000000 b w ddr4 initial value access address : 000607 h 00000000 b w ddr5 initial value access address : 000606 h 00000000 b w ddr6 initial value access address : 000605 h 00000000 b w ddr8 initial value access address : 00060b h - 0000000 b w ddrc initial value access address : 0000d3 h 00000000 b r/w ddrd initial value access address : 0000d2 h 00000000 b r/w ddre initial value access address : 0000d1 h 00000000 b r/w ddrf initial value access address : 0000d0 h 00000000 b r/w ddrg initial value access address : 0000d7 h - - 000000 b r/w ddrh initial value access address : 0000d6 h - - - - - 000 b r/w ddri initial value access address : 0000d5 h - - 000000 b r/w ddrj initial value access address : 0000d4 h - - 000000 b r/w ddrk initial value access address : 0000db h 00000000 b r/w ddrl initial value access address : 0000da h 00000000 b r/w 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 7654 321 0 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 p86 ? p85 p84 p83 p82 p81 p80 7654 321 0 pc6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 7654 321 0 pd6 pd7 pd5 pd4 pd3 pd2 pd1 pd0 7654 321 0 pe6 pe7 pe5 pe4 pe3 pe2 pe1 pe0 7654 321 0 pf6 pf7 pf5 pf4 pf3 pf2 pf1 pf0 7654 321 0 ? ? pg5 pg4 pg3 pg2 pg1 pg0 7654 321 0 ? ???? ph2 ph1 ph0 7654 321 0 ? ? pi5 pi4 pi3 pi2 pi1 pi0 7654 321 0 ? ? pj5 pj4 pj3 pj2 pj1 pj0 7654 321 0 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0 7654 321 0 pl6 pl7 pl5 pl4 pl3 pl2 pl1 pl0
mb91133/mb91f133 47 ? pull up control register (pcr) ? open-drain control register (odcr) pcr6 to j carry out pull-up resistance control of the i/o ports handled. pcr = 0 : pull-up resistance turned off pcr = 1 : pull-up resistance turned on pcr6 initial value access address : 000631 h 00000000 b r/w pcrc initial value access address : 0000c3 h 00000000 b r/w pcrd initial value access address : 0000c2 h 00000000 b r/w pcre initial value access address : 0000c1 h - - - - - - 00 b r/w pcrh initial value access address : 0000c6 h - - - - - 000 b r/w pcri initial value access address : 0000c5 h - - 000000 b r/w pcrj initial value access address : 0000c4 h - - 000000 b r/w 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 pc6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 7654 321 0 pd6 pd7 pd5 pd4 pd3 pd2 pd1 pd0 7654 321 0 ? ????? pe1 pe0 7654 321 0 ? ???? ph2 ph1 ph0 7654 321 0 ? ? pi5 pi4 pi3 pi2 pi1 pi0 7654 321 0 ? ? pj5 pj4 pj3 pj2 pj1 pj0 ocrh to j carry out open-drain control in output mode of the i/o ports handled. ocr = 0 : standard output port in output mode ocr = 1 : open-drain output port in output mode this has no meaning in input mode (output hi-z) . ocrh initial value access address : 0000ca h - - - - - 000 b r/w ocri initial value access address : 0000c9 h - - 000000 b r/w ocrj initial value access address : 0000c8 h - - 000000 b r/w 7654 321 0 ? ???? ph2 ph1 ph0 7654 321 0 ? ? pi5 pi4 pi3 pi2 pi1 pi0 7654 321 0 ? ? pj5 pj4 pj3 pj2 pj1 pj0
mb91133/mb91f133 48 ? analog input control register (aicr) aick controls each pin of the i/o ports handled as follows. aic = 0 : analog input mode aic = 1 : port input mode set to 0 when reset. aick initial value access address : 0000cf h 00000000 b r/w 7654 321 0 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0
mb91133/mb91f133 49 3. 8/16-bit up/down counter / timer 8/16-bit up/down counter / timer is configured of event input pins 6, 8-bit up/down counters 2, 8-bit reload / compare registers 2 and their control circuits. ? characteristics of 8 / 16-bit up / down counter / timer ? counting from (0) d to (256) d is possible using an 8-bit counting register. (counting from (0) d to (65535) d is possible in 16-bit 1 operation mode.) ? 4 types of counting mode can be selected by the count clock ? selection can be made from two types of internal clock as the count clock in timer mode. ? detection edge of the external pin input signals can be selected in up/down count mode. ? phase difference count mode is suited to count encoders such as motors. turning angle and turning number, etc., can easily and accurately be counted by separately inputting phase a, b and z outputs of the encoder. ? selection can be made from two function types for the zin pin (valid for all modes) . ? compare and reload functions are featured, and each function can be used alone or in combination. up/down counting with random width can be carried out using both functions in combination. ? the count direction directly before can be identified by the count direction flag. ? generation of interruptions in case of compared match, reload (underflow) or overflow and in cases where the count direction is changed can be controlled separately.
mb91133/mb91f133 50 ? block diagram cge1 cge0 edge/level detection c/gs carry cms1 cms0 ces1 ces0 cite udie udf1 udf0 cdcf cfie count clock interruption output rcut reload control counter clear up/down count clock selection ucre 8 bit 8 bit data bus reload / compare register 0 (rcr0) up/down count register 0 (udcr0) rlde udcc cmpf udff ovff clks cstr pre-scalar ain0 bin0 zin0 8 / 16 - bit up / down counter / timer ( ch0 )
mb91133/mb91f133 51 cge1 cge0 c/gs carry count clock interruption output cite udie udf1 up/down count clock selection udf0 cdcf cfie rcut reload control counter clear edge/level detection ucre rlde udcc cmpf udff ovff clks cstr pre-scalar ain1 bin1 zin1 cms1 cms0 ces1 ces0 m16e 8 bit 8 bit data bus reload / compare register 1 (rcr1) up/down count register 1 (udcr1) 8 / 16 - bit up / down counter / timer ( ch1 )
mb91133/mb91f133 52 ? register list up/down count register ch0 (udcr0) up/down count register ch1 (udcr1) reload compare register ch0 (rcr0) reload compare register ch1 (rcr1) counter status register ch0, 1 (csr0, 1) counter control register ch0, 1 (ccrl0, 1) counter control register ch0 (ccrh0) counter control register ch1 (ccrh1) bit address : 000087 h bit address : 000086 h bit address : 000085 h bit address : 000084 h bit address : 00008b h 00008f h bit address : 000089 h 00008d h bit address : 000088 h bit address :00008c h 15 8 udcr1 70 31 24 rcr1 udcr0 rcr0 ? ccrh0 csr0 ccrl0 ? ccrh1 csr1 ccrl1 23 16 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d00 15 14 13 12 11 10 9 8 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d00 15 14 13 12 11 10 9 8 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 cite cstr udie cmpf ovff udff udf1 udf0 7654 321 0 ctut ? ucre rlde udcc cgsc cge1 cge0 15 14 13 12 11 10 9 8 cdcf m16e cfie clks cms1 cms0 ces1 ces0 15 14 13 12 11 10 9 8 cdcf ? cfie clks cms1 cms0 ces1 ces0
mb91133/mb91f133 53 4. 16-bit reload timer the 16-bit timer is configured with a 16-bit down counter, 16-bit reload register, pre-scalar to prepare the internal count clock and control register. selection can be made from three types of internal clocks (machine clock 2 / 8 / 32 cycles) as the input clock. dma transfer can be initiated by interruption. the mb91133/mb91f133 features a 5-channel timer. ? block diagram channel 2to output of the reload timer is connected to the a/d converter inside the lsi. thus, a/d conversion can be started up at the cycle set in the reload register. reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 r - bus 3 2 uf reload clock selector 16-bit reload register 16-bit down counter in ctl. f 2 f 2 f 2 1 35 3 exck pre-scalar clear gate 2 re-trigger irq pwm (ch0, ch1) a/d (ch2)
mb91133/mb91f133 54 5. ppg timer the ppg timer can efficiently output accurate pwm waveforms. the mb91130 series features a 6-channel ppg timer. ? ppg timer characteristics ? each channel is configured with a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty setting buffer and pin control area. ? selection can be made from four types of count clocks for 16-bit down counters. internal clock f , f 4, f 16, f 64 ? counter values can be initialized to ffff h by resetting and counter borrowing. ? pwm output is available per channel. ? register outline cycle setting register : reloading register with buffer duty setting register : compare register with buffer transfer from buffer is carried out by counter borrowing. ? pin control outline set to 1 by duty match. (priority) resets to 0 by counter borrowing. all l (or h) can simply be output by using the output values fixing mode. polarization can also be specified. ? interruption request can be generated by selecting from the following combinations. initiation of this timer counter borrow generation (cycle match) duty match generation counter borrow generation (cycle match) or duty match generation dma transfer can be initiated by the above interruption requests. ? simultaneous initiation of a number of channels can be set by software or other interval timers. re-start during operation can also be set.
mb91133/mb91f133 55 ? block diagram 4 4 pwm0 16-bit reload timer ch0 general control register 1 (factor selection) 16-bit reload timer ch1 general control register 2 external trg0 to 3 external trg4 external trg5 trg input pwm timer ch0 trg input pwm timer ch1 trg input pwm timer ch2 trg input pwm timer ch3 pwm1 pwm2 pwm3 pwm4 pwm5 pwm timer ch4 pwm timer ch5 overall block diagram of ppg time
mb91133/mb91f133 56 1 / 1 1 / 4 1 / 16 1 / 64 ck pwm output pcsr ppg mask enable trg input soft trigger reverse bit load pdut cmp interruption selection edge detection start borrow pre-scalar 16-bit down counter peripheral system clock s r q irq block diagram of ppg timer for 1 channel
mb91133/mb91f133 57 ? register list (continued) gcn1 gcn2 ptmr pcsr pdut pcnh pcnl ptmr pcsr pdut pcnh pcnl ptmr pcsr pdut pcnh r/w r/w r w w r/w r w w r/w r w w r/w 15 address 0 000000df h 000000e6 h 000000ee h 000000f6 h pcnl ptmr pcsr pdut pcnh pcnl r w w r/w general control register 1 general control register 2 ch0 timer register ch0 peripheral setting register ch0 duty setting register ch0 control status register ch1 timer register ch1 peripheral setting register ch1 duty setting register ch1 control status register ch2 timer register ch2 peripheral setting register ch2 duty setting register ch2 control status register ch3 timer register ch3 peripheral setting register ch3 duty setting register ch3 control status register 000000fe h 000000dc h 000000e4 h 000000ec h 000000f4 h 000000fc h 000000e2 h 000000ea h 000000f2 h 000000fa h 000000e0 h 000000e8 h 000000f0 h 000000f8 h
mb91133/mb91f133 58 (continued) 15 0 ptmr pcsr pdut pcnh r w w r/w 00000106 h pcnl ptmr pcsr pdut pcnh pcnl r w w r/w ch4 peripheral setting register ch4 duty setting register ch4 control status register ch5 timer register ch5 peripheral setting register ch5 duty setting register ch5 control status register 0000010e h 00000104 h 0000010c h 00000102 h 0000010a h 00000100 h 00000108 h address ch4 timer register
mb91133/mb91f133 59 6. multifunction timer the multifunction timer unit is configured of a 16-bit freerun timer 1, 16-bit output compare 8, 16-bit input capture 4, 16-bit ppg timer 6 ch and waveform generation area modules. 12 independent waveform outputs based on a 16-bit free-run timer are possible using this function and measurement of input pulse width and external clock cycle is also possible. ? multifunction timer configuration ? 16-bit free-run timer ( 1) the 16-bit free-run timer consists of a 16-bit up counter, control register, 16-bit compare clear register and pre-scalar. output values of this counter are used as the base timer for output compare and input capture. counter operation clocks can be selected from six types. six types of internal clocks ( f 2, f 4, f 8, f 16, f 32, f 64) f : machine clock interruption can be generated by overflow of the counter value and a compared match with compare clear register. (mode setting is required for a compared match.) counter value can be initialized to 0000 h by a compared match with the reset, software clear or the compare clear register. ? output compare ( 8) output compare is configured of 16-bit compare register 8, latch for compare output and control register. interruption can be generated as well as reversing output level when the 16-bit free-run timer value and compare register value match. 8 compare registers can be operated independently. output pins and interruption flags support each compare register. output pins can be controlled by pairing two compare registers. output pins are reversed using two compare registers. initial value of each output pin can be set. interruption can be generated by matching compare. ? input capture ( 4) input capture is configured with four independent external input pins , supported capture and control register. 16-bit free-run timer value is held in the capture register by detecting the random edge of signals that are input by the external input pin, and interruption can simultaneously be generated. valid edges (rising edge, falling edge, both edges) of external input signals can be selected. four input captures can be operated independently. interruption can be generated by the valid edges of external input signals. ? 16-bit ppg timer ( 6) refer to ppg timer
mb91133/mb91f133 60 ? waveform generation area the waveform generation area is configured with 8-bit timer 3, 8-bit reload register 3, timer control register 3 and 8-bit waveform control register. this control circuit controls the waveform of the 16-bit ppg timer and real-time output, and dc chopper output and non-overlapping 3-phase waveform output to be used for inverter control are possible. non-overlapping pulse output of the ppg timer is possible by setting dead time of the 8-bit timer (dead time timer function) . real timer output is operated by the 2-channel mode and non-overlapping output of the waveform is possible by setting the dead time of the 8-bit timer (dead time timer function) . operation of ppg timer can easily be started/stopped by generating a gate signal for the ppg timer operation through match detection of real-time output compare (gate function). the 8-bit timer is operated by match detection of real-time output compare, and operation of the ppg timer can easily be started/stopped by generating a gate signal for the ppg timer until the 8-bit timer is stopped (gate function) . pin output can be forcibly controlled by input to the dtti pin. pins can be controlled externally even if oscillations stop due to lack of clocks for inputs to this pin. (each pin level can be set by the program .) if this function is used, the port should be set to output (ddr = 1) and the output value should be described in the pdr beforehand.
mb91133/mb91f133 61 ? block diagram f ivf r-bus ivfe 16-bit free-run timer compare register 0/2/4 compare circuit compare register 1/3/5 compare circuit capture data register 0/2 capture data register 1/3 16-bit compare clear register (ch. 6 compare register) stop mode sclr clk2 clk1 clk0 cycle device iclr iop1 iop0 ioe1 ioe0 icp0 icp1 ice0 ice1 eg11 eg10 eg01 eg00 in 0/2 in 1/3 cmod rt0/2/4 clock interruption interruption interruption interruption interruption interruption tq rt1/3/5 to waveform generation area to waveform generation area tq icre ms13 ~ 0 compare circuit edge detection edge detection block diagram of ppg timer for 1 channel
mb91133/mb91f133 62 r - bus f dck2 cycle device dtti control circuit waveform generation area dead time generation clock 8-bit timer 8-bit timer register 0 compare circuit selector selector waveform generation area dead time generation 8-bit timer 8-bit timer register 1 compare circuit selector selector waveform generation area dead time generation 8-bit timer 8-bit timer register 2 compare circuit selector selector dck1 dck0 tmd1 tmd0 nrsl dtil dtie dtti gate 0/1 to0 to1 rto0/u rto1/x rto2/v rto3/y rto4/w rto5/z u x to2 to3 v y to4 to5 w z gate 2/3 gate 4/5 rt4 rt5 rt2 rt3 rt0 rt1 block diagram of waveform generation area
mb91133/mb91f133 63 ? registers list 15 address 8 7 0 ipcp occp ocs tcdt tccs ics tmrr stgcr dtcr (r) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 000044 h to 4b h 00004d h , 4f h 000054 h to 63 h 000064 h to 6b h 00006c h , 6d h 00006e h , 6f h 0000ad h , af h b3 h 0000b1 h 0000ac h , ae h b2 h
mb91133/mb91f133 64 7. external interruption the external interruption control area is the block that controls the external interruption requests input in int0 to int23. the level of request to be detected can be selected from h, l, rising edge or falling edge. ? block diagram ? register list 24 r-bus interruption permission register gate interruption requests factor f/f edge detection circuit interruption factor register request level setting register 24 48 24 24 int0 to int23 external interruption permission register (enir) external interruption factor register (eirr) request level setting register (elvr) there are three sets of the above registers (for 8 channels) for a total of 24 channels. bit bit bit bit 15 14 13 12 11 10 9 8 er6 er7 er5 er4 er3 er2 er1 er0 15 14 13 12 11 10 9 8 er6 er7 er5 er4 er3 er2 er1 er0 7654 321 0 la3 lb3 lb2 la2 lb1 la1 lb0 la0 15 14 13 12 11 10 9 8 la7 lb7 lb6 la6 lb5 la5 lb4 la4
mb91133/mb91f133 65 8. delay interruption module the delay interruption module generates interruptions for task switching. interruption requests to the cpu can be generated / cancelled using software with this module. ?block diagram refer to 9.(2) block diagram of interruption controller for the block diagram of the delay interruption generation area. ? register list address : 00000430 h dicr bit 7 6 5 4 3 2 1 0 r/w ? ? ? ???? dlyi
mb91133/mb91f133 66 9. interruption controller the interruption controller carries out interruption reception and arbitration. ? hardware configuration of the interruption controller this module consists of the following items. ? icr register ? interruption priority judgement circuit ? interruption level, interruption number (vector) generation area ? cancellation request generation area for hold request ? major interruption controller functions this module has the following functions. ? detection of interruption requests ? priority grade judgement (depending on the level and number) ? transferring interruption level of factors for the judgement results (to cpu) ? transferring interruption number of factors for the judgement results (to cpu) ? recovery instruction from stop mode by generating interruption ? cancellation of hold request to the bus master ? resetting interruption factors there are restrictions between reti instructions and those for resetting interruption factors in the interruption routine.
mb91133/mb91f133 67 ? block diagram im int0 or nmi ri00 ri47 (dlyirq) dlyi 4 5 priority grade judgement 6 hldreq (holding request) generation of level / vector vector judgement level4 to 0 hldcan vct5 to 0 icr00 level judgement nmi processing icr47 r-bus note : dlyi shown in the figure indicates delay interruption area. (refer to the chapter on the delay interruption module for details.) into is the wake-up signal to the clock control area in case of sleep or stop. hldcan is the bus vacation request signal to bus masters other than the cpu. there is no nmi function in this model.
mb91133/mb91f133 68 ? register list (continued) address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : bit 7 6 5 4 3 2 1 0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 icr00 icr01 icr02 icr03 icr04 icr05 icr06 icr07 icr08 icr09 icr10 icr11 icr12 icr13 icr14 icr15 icr16 icr17 icr18 icr19 icr20 icr21 icr22 icr23 icr24 icr25 icr26 icr27 icr28 icr29 icr30 icr31 00000400 h 00000401 h 00000402 h 00000403 h 00000404 h 00000405 h 00000406 h 00000407 h 00000408 h 00000409 h 0000040a h 0000040b h 0000040c h 0000040d h 0000040e h 0000040f h 00000410 h 00000411 h 00000412 h 00000413 h 00000414 h 00000415 h 00000416 h 00000417 h 00000418 h 00000419 h 0000041a h 0000041b h 0000041c h 0000041d h 0000041e h 0000041f h r/w r/w r/w r/w
mb91133/mb91f133 69 (continued) address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : bit 7 6 5 4 3 2 1 0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 ? ??? icr3 icr2 icr1 icr0 r/w r/w r/w r/w ? ??? lvl3 lvl2 lvl1 lvl0 r/w r/w r/w r/w icr32 icr33 icr34 icr35 icr36 icr37 icr38 icr39 icr40 icr41 icr42 icr43 icr44 icr45 icr46 icr47 hrcl 00000420 h 00000421 h 00000422 h 00000423 h 00000424 h 00000425 h 00000426 h 00000427 h 00000428 h 00000429 h 0000042a h 0000042b h 0000042c h 0000042d h 0000042e h 0000042f h 00000431 h
mb91133/mb91f133 70 10. clock generation area (low power consumption mechanism) clock generation area is a module with the following functions. ? cpu clock generation (including gear function) ? peripheral clock generation (including gear function) ? reset generation and holding factors ? standby function (including hardware standby) ? pll (phase locked loop) is built in ? register list 7 reset factor / watchdog cycle control register standby control register dma request blocking register time base timer clear register gear control register watchdog reset generation postponement register pll / 32-k clock control register address rsrr/wtcr stcr pdrr ctbr 000480 h 000481 h 000482 h 000483 h gcr wpr pctr 000484 h 000485 h 000488 h 0
mb91133/mb91f133 71 ? block diagram x0 count clock x1 x0a cpu clock internal bus clock internal peripheral clock stop status sleep status cpu hold request internal reset 32-khz selection circuit [ gear control area ] [ stop/sleep control area ] [ reset factor circuit ] [ watchdog control area ] x1a v cc 3 gnd rst pin m p x pll stcr register pdrr register rsrr register wpp register watchdog f/f time base timer ctbr register internal interruption internal reset dma request power on detection circuit 1 / 2 cpu gear peripheral gear internal clock generation circuit status transfer control circuit reset generation f/f gcr register oscillation circuit oscillation circuit r
mb91133/mb91f133 72 11. 8-/10-bit a/d converter the 8-/10-bit a/d converter features functions that convert analog input voltages to 10- or 8-bit digital values using the rc sequential comparison conversion method. the input signal is selected from 8-channel analog input pins and three types of conversion initiation can be selected from software, internal clock, or external pin trigger. ? characteristics of 8-/10-bit a/d converter the a/d conversion function for converting analog voltages (input voltages) input into the analog input pins to digital values has the following characteristics. ? conversion time is minimum 5.0 m s (including sampling time when machine clock is 33 mhz) . ? conversion method is rc sequential comparison conversion method with sample holding circuit. ? 10- or 8-bit resolution can be selected. ? analog input pin can be selected from 8 channels using the program. ? interruption request can be generated when a/d conversion ends. ? data is not lost even during continuous conversion as conversion data protection function works while inter- ruptions are permitted. ? initiation factors for conversion can be selected from software, 16-bit reload timer 2 (rising edge) , or external pin trigger (l level detection) . there are three types of conversion modes. table 13.1-1 conversion modes of 8-/10-bit a/d converter conversion modes single conversion operation scan conversion operation single conversion mode converts the specified channel (1 channel only) once and ends. converts a series of channels (up to 8 channels can be specified) once and ends. consecutive conversion mode repeatedly converts the specified channel (1 channel only) . repeatedly converts a series of channels (up to 8 channels can be specified) . stop conversion mode suspends after converting the specified channel (1 channel only) once and waits until the next one is initiated. converts a series of channels (up to 8 channels can be specified) but is suspend- ed between each channel conversion and waits until the next one is initiated.
mb91133/mb91f133 73 ? block diagram of 8-/10-bit a/d converter the 8-/10-bit a/d converter is configured with the following 9 blocks. ? a/d control status register (adcs1, 2) ? a/d data register (adcr) ? clock selector (input clock selector to initiate a/d conversion) ? decoder ? analog channel selector ? sample holding circuit ? d/a converter ? comparator ? control circuit ? block diagram ? register list f mp comparator decoder input circuit an0 an1 an2 an3 an4 an5 an6 an7 sample and holding circuit operation clock adcr adcs1 , 2 pre-scalar 16-bit reload timer 2 external pin trigger av ss d/a converter data register a/d control register 1 a/d control register 2 sequential comparison register avr av ss r - bus 15 14 13 12 11 10 9 8 76543210 0000cf h 00003a h adcs1 000038 h aick adcs0 adcr
mb91133/mb91f133 74 12. 8-bit d/a converter the 8-bit d/a converter is an r-2r type d/a converter with 8-bit resolution. ? characteristics of the 8-bit d/a converter the mb81130 series features a 3-channel d/a converter and output control can be carried out individually by the d/a control register. ? block diagram of 8-bit d/a converter the 8-bit d/a converter is configured with the following three blocks. ? 8-bit resistance ladder ? data register ? control register ? block diagram da27 da27 to da20 da17 to da10 da07 to da00 davc da20 da output da output da output dae dae dae standby control standby control standby control da17 davc da10 da07 davc da00 r - bus
mb91133/mb91f133 75 ? 8-bit d/a converter pins d/a converter pins are dedicated pins. ? registers of 8-bit d/a converter the 8-bit d/a converter has the following two registers. d/a control register (dacr0, 1, 2) d/a data register (dadr2, 1, 0) ? register list d/a converter data register 0 d/a converter data register 1 d/a converter data register 2 d/a control register 0 d/a control register 1 d/a control register 2 bit dadr0 00000ab h bit dadr1 00000aa h bit dadr2 00000a9 h bit dacr0 00000a7 h bit dacr1 00000a6 h bit dacr2 00000a5 h 7654 321 0 da06 da07 da05 da04 da03 da02 da01 da00 15 14 13 12 11 10 9 8 da16 da17 da15 da14 da13 da12 da11 da10 23 22 21 20 19 18 17 16 da26 da27 da25 da24 da23 da22 da21 da20 7654 321 0 ? ? ? ???? dae0 15 14 13 12 11 10 9 8 ? ? ? ???? dae1 23 22 21 20 19 18 17 16 ? ? ? ???? dae2
mb91133/mb91f133 76 13. 4-bit level comparator the 4-bit level comparator is the module that compares input levels (large/small) and compares the size of the analog input voltage with 4-bit digital values. ? functions of the 4-bit level comparator compares analog voltage that has been input to the analog input pins (input voltage) with 4-bit digital value and has the following characteristics. ? conversion time is minimum 1 m s (including sampling time) . ? sampling time is minimum 0.5 m s. ? interruption requests can be generated when analog comparison ends. ? interruption of 4-bit level comparator table 15.1-1 interruption and dmac of 4-bit level comparator : initiation is impossible interruption number interruption control register offset tbr default address dmac register name address #61 (3d h ) icr45 00042d h 308 h 000fff08 h
mb91133/mb91f133 77 ? block diagram of 4-bit level comparator the 4-bit level comparator is configured with the following three blocks. ? comparator ? 4-bit resistance ladder ? control register ? block diagram f an7 interruption sample & holding circuit av cc rd3 - 0 comparator reload timer operation clock avr 4-bit d/a (resistance ladder) av ss fr30 r - bus cplv int inte cpen
mb91133/mb91f133 78 ? registers of 4-bit lev el comparator ? register list control register (lvlc) bit 0000018 h attribute initial value 0000-0018 h bit 31 bit 24 lvlc bit 23 bit 16 r/w ( x ) r/w ( x ) r/w ( x ) r/w ( 0 ) r/w ( 0 ) r/w ( 0 ) r/w ( 0 ) 31 30 29 28 27 26 25 24 rd2 r/w ( x ) rd3 rd1 rd0 cplv int inte cpen
mb91133/mb91f133 79 14. uart uart is the general-purpose serial data communications interface to carry out synchronous or asynchronous communication (start-stop synchronization) with external systems. it has a master/slave-type communications function (multiprocessor mode: supporting only master side) as well as normal bi-directional communications function (normal mode). ? uart functions uart is the general-purpose serial data communications interface that sends and receives serial data to/from other cpus and peripheral equipment, and has functions shown in table 16.1-1. table 16.1-1 uart functions note : start / stop bits are not added by uart and only data is transferred. table 16.1-2 uart operations mode ? : setting is impossible *1 : + 1 is address / data selection bit (a/d) to be used to control communications. *2 : 1-bit only can be detected for stop bit in case of reception. operations mode data length synchronization method stop bit length without parity with parity 0 normal mode 7-bit or 8-bit asynchronous 1-bit or 2-bit *2 1 multiprocessor mode 8 + 1* 1 ? asynchronous 2normal mode 8 ? synchronous n/a functions data buffer full-duplex double buffer transfer mode ? clock synchronous (without start-stop bit) ? clock asynchronous (start-stop cycle) baud rate ? dedicated baud rate generator is available. can be selected from 8 types. ? external clock input is possible. ? internal clock (internal clocks that are provided from 16-bit reload timer support- ing each channel can be used.) data length ? 7-bit (in case of asynchronous normal mode only) ?8-bit signal method non return to zero (nrz) method reception error detection ?framing error ?overrun error ? parity error (impossible in case of multiprocessor mode) interruption request ? reception interruption (reception completion, reception error detection) ? transmission interruption (transmission completion) master/slave-type communications function (multiprocessor mode) communication between 1 (master) and n (slaves) is possible (only supports master side)
mb91133/mb91f133 80 ? uart block diagram uart is configured with the following 11 blocks. ? block diagram ? clock selector ? mode register (smr0 to 4) ? reception control circuit ? control register (scr0 to 4) ? transmission control circuit ? status register (ssr0 to 4) ? reception status judgement circuit ? input data register (sidr0 to 4) ? shift register for reception ? output data register (sodr0 to 4) ? sift register for transmission md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a / d rec rxe txe pe ore fre rdrf tdre bds rie tie sidr0 ~ 4 control bus reception interruption signals #26 to 30 * reception interruption signals #31 to 35 * dedicated baud rate generator 16-bit reload timer sodr0 ~ 4 pin pin reception clock transmission clock reception control circuit transmission control circuit start bit detection circuit reception bit counter reception parity counter shift register for reception transmission start circuit transmission bit counter transmission parity counter shift register for transmission clock selector reception status judgement circuit pin smr0 to 4 registers scr0 to 4 registers ssr0 to 4 registers reception ends internal data bus transmission starts reception error generation signal (to cpu) * : interruption number
mb91133/mb91f133 81 ? block diagram of uart pins ? register list data bus pdr read 0 1 0 1 pin pdr ddr odcr pcr pdr ddr odcr pcr : port data register : data direction register : open-drain control register : pull-up control register resource input resource output resource output permission ch0 : 0000_001e h , 1f h ch1 : 0000_0022 h , 23 h ch2 : 0000_0026 h , 27 h ch3 : 0000_0072 h , 73 h ch4 : 0000_0076 h , 77 h ch0 : 0000_001c h , 1d h ch1 : 0000_0020 h , 21 h ch2 : 0000_0024 h , 25 h ch3 : 0000_0070 h , 71 h ch4 : 0000_0074 h , 75 h ch0 : 0000_007a h ch1 : 0000_0078 h ch2 : 0000_007e h ch3 : 0000_007c h ch4 : 0000_0082 h bit 15 control register (scr) mode register (smr) status register (ssr) input/output data register (sidr/sodr) communications pre-scalar control register (cdcr) vacant address bit 8 bit 7 bit 0
mb91133/mb91f133 82 15. dma controller the dma controller is the built-in module of the mb91130 series that carrie out direct memory access (dma) transfers. ? characteristics of the dma controller ? 8 channels ? 3 transfer mode types : single/block transfer, burst transfer, continuous transfer ? transfer between overall address areas ? maximum 65,536 transfers ? interruption function when transfer ends ? increase/decrease in transfer addresses can be selected using software ? 3 external transfer request input/output pins and 3 external transfer end output pins ? block diagram dreq0 to dreq2 built-in resource transfer request dack0 to dack2 eop0 to eop2 interruption request dpdp switcher dacsr data bus datcr blk dec data buffer inc / dec blk mode dmact sadr dadr 3 edge / level detection circuit 3 sequencer 3 3 8 5
mb91133/mb91f133 83 ? register list (in dmac : dmac internal registers) (on ram : dma descriptors) 00000200 h 00000204 h 00000208 h dpdp dacsr datcr 31 0 bit 31 bit 0 dpdp + 0 h dpdp + 0c h dpdp + 54 h dma ch0 descriptor dma ch1 descriptor dma ch7 descriptor
mb91133/mb91f133 84 16. bit search module the bit search module searches for 0, 1 or change points on data that has been written in the input register, and returns the detected bit position. ? block diagram ? register list d-bus input latch changing to 1 detection data bit search circuit detection results address decoder detection mode address : data register for 0 detection address : data register for 1 detection address : data register for change point detection address : detection results register 31 bsd0 bsd1 bsdc bsrr 000003f0 h 000003f4 h 000003f8 h 000003fc h 0
mb91133/mb91f133 85 17. flash memory the mb91fv130 / mb91f133 have a 254-kb (2 mbit) capacity and feature a flash memory that can write each half-word (16 bits) using the fr-cpu, delete individual sectors sector and delete groups of sectors together using a single 3-v power source. ? outline of flash memory this is a built-in 3-v 254-kb flash memory. this flash memory is the same as our 2-mbit (256 k 8 / 128 k 16) flash memory mbm29lv400c and writing is possible from outside the device using a rom writer. if used as a built-in rom of the fr-cpu, as well as having an equivalent function to the mbm29lv400c, instruc- tions / data can be read per word (32 bits) and high-speed operation of the device can be realized. refer to the mbm29lv400c data sheet as well as this manual. the following functions can be realised in mb91fv130 / mb91f133 by combining the flash memory macro and fr-cpu interface circuits. ? functioning as memory for cpu program / data storage access is possible with 32-bit bus width when used as rom reading / writing and erasing (automatic program algorithm * ) are possible using cpu ? mbm29lv400c-equivalent function of single flash memory products reading / writing and erasing (automatic program algorithm * ) are possible using rom writer a case where this flash memory is used from fr-cpu is described in this section. refer to the rom writer manual separately for details if this flash memory is used from rom writer. * : automatic program algorithm = embedded algorithm tm embedded algorithm tm is the trademark of advanced micro device. ? block diagram rdy/busy reset byte oe we ce fa18 - 0 address buffer data buffer ca18 - 0 interruption request bus control signal inte rdyint rdy we fr-c bus (instruction / data) rising edge detection control signal generation cd31 - 0 di15 - 0 flash memory 2 mbit (254 k 8/127 k 16) do31 - 0
mb91133/mb91f133 86 ? memory map flash memory mode and cpu mode for address mapping of flash memory are different. mapping under each mode is shown as follows. ? memory map in flash memory mode ? memory map in cpu memory mode sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 ( san : sector address n ) 2 m-flash memory image 0fffff h 0c0000 h 010000 h 000000 h ( san : sector address n ) cpu mode 0fffff h 0fffff h sa4 sa9 sa3 sa8 sa2 sa7 sa1 sa6 sa0 flash memory area status register ram area 2 kbyte sa5 0f8000 h 0f4000 h 0f0000 h 0e0000 h 0c0000 h 0c0800 h 0c0000 h 0007c0 h 000000 h 0c0800 h
mb91133/mb91f133 87 ? sector address table ? registers of flash memory there are two types of flash memory registers, namely status register (flcl) and wait register (fwtc). ? status register (flcr) (cpu mode) this register indicates the operation status of the flash memory. it controls interruption to the cpu and writing to the flash memory. access is possible only in cpu mode. this register must not be accessed under read / modify / write instructions. ? wait register ( fwtc) carries out wait control of the flash memory in cpu mode. also, controls access to high-speed reading (33mhz) of flash memory. configuration of wait register (fwtc) is as follows : note : fach bit should be set to 1 or wtc1/0 should be set to 01b to operate machine clocks of cpus exceeding 25 mhz. sector address address area position of bit handled sector capacity sa5 000c0802, 3h to 000dfffe, fh (lsb side 16 bit) bit 15 to 0 63 kbyte sa6 000e0002, 3h to 000efffe, fh (lsb side 16 bit) bit 15 to 0 32 kbyte sa7 000f0002, 3h to 000f3ffe, fh (lsb side 16 bit) bit 15 to 0 8 kbyte sa8 000f4002, 3h to 000f7ffe, fh (lsb side 16 bit) bit 15 to 0 8 kbyte sa9 000f8002, 3h to 000ffffe, fh (lsb side 16 bit) bit 15 to 0 16 kbyte sa0 000c0800, 1h to 000dfffc, dh (msb side 16 bit) bit 31 to 16 63 kbyte sa1 000e0000, 1h to 000efffc, dh (msb side 16 bit) bit 31 to 16 32 kbyte sa2 000f0000, 1h to 000f3ffc, dh (msb side 16 bit) bit 31 to 16 8 kbyte sa3 000f4000, 1h to 000f7ffc, dh (msb side 16 bit) bit 31 to 16 8 kbyte sa4 000f8000, 1h to 000ffffc, dh (msb side 16 bit) bit 31 to 16 16 kbyte r/w ( 0 ) r/w ( 0 ) r ( x ) ? ( x ) ? ( x ) ? ( x ) r/w ( 0 ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdyint r/w ( 0 ) inte we rdy ?? lpm 0007c0 h ? ? ( ? ) ? ( ? ) ? ( ? ) ? ( ? ) w ( 0 ) r/w ( 0 ) r/w ( 0 ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ( ? ) ???? fach wtc1 wtc0 0007c4 h
mb91133/mb91f133 88 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : care must be taken that this does not exceed v cc 5 + 0.3 v when the power is turned on. also, care must be taken that av cc does not exceed v cc 5 when the power is turned on. av cc should be set at the same electrical potential as v cc 5. *2 : peak value of the pin concerned is regulated as the maximum output current. *3 : average current within 100 ms flowing in the pin concerned is regulated as the average output current. *4 : average current within 100 ms flowing in all pins concerned is regulated as the average total output current. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min. max. power voltage v cc 5v ss - 0.3 v ss + 6.5 v power voltage v cc 3v ss - 0.3 v ss + 3.8 v analog power voltage av cc v ss - 0.3 v ss + 6.5 v *1 standard analog voltage avrh v ss - 0.3 v ss + 6.5 v *1 input voltage v i5 v ss - 0.3 v cc 5 + 0.3 v input voltage v i3 v ss - 0.3 v cc 3 + 0.3 v x0, x1, x0a, x01a analog pin input voltage v ia v ss - 0.3 av cc + 0.3 v output voltage v o v ss - 0.3 v cc 5 + 0.3 v maximum l level output current i ol ? 10 ma *2 average l level output current i olav ? 4ma*3 maximum total l level output current s i ol ? 100 ma average l level total output current s i olav ? 50 ma *4 maximum h level output current i oh ?- 10 ma *2 average h level output current i ohav ?- 4ma*3 maximum total h level output current s i oh ?- 50 ma average h level total output current s i ohav ?- 20 ma *4 electricity consumption p d ? 500 mw storage temperature tstg - 55 + 150 c
mb91133/mb91f133 89 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power voltage common v cc 5 4.5 5.5 v under normal operation eva flash v cc 3 3.0 3.6 v under normal operation 3.0 3.6 ram status kept in the case of stop mask rom v cc 3 2.7 3.6 v under normal operation 2.7 3.6 v ram status kept in the case of stop analog power voltage av cc v ss + 4.5 v ss + 5.5 v standard analog voltage avrh av ss - 0.3 av cc v operating temperature t a 0 + 70 c in external rom external bus / internal rom external bus modes t a - 40 + 70 c in single-chip mode
mb91133/mb91f133 90 3. dc characteristics (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) *1 : refer to pin function descriptions *2 : in case of clk pin output only (c l = 80 pf) *3 : output pin open parameter sym- bol pin name conditions value unit re- marks min. typ. max. h level input voltage v ih input excluding following (*1) ? 0.7 v cc 5 ? v cc 5 + 0.3 v v ihs *1 hysteresis input pin ? v cc 5 - 0.4 ? v cc 5 + 0.3 v l level input voltage v il input excluding following (*1) ? v ss - 0.3 ? 0.2 v cc 5v v ils *1 hysteresis input pin ? v ss - 0.3 ? v ss + 0.4 v h level output voltage v oh ? v cc 5 = 5.0 v, i oh = - 4.0 ma 2.6 ?? v l level output voltage v ol ? v cc 5 = 5.0 v, i ol = 4.0 ma ?? 0.6 v input leak current i li ? v cc 5 = 5.0 v, v ss < v i < v dd - 5 ? 5 m a pull up resistance value r pull rst ?? 50 ? k w power current i cc 5v cc 5v cc 5 = 5.0 v ? 15 20 ma *2 i cc 3v cc 3v cc 3 = 3.0 v ? 50 100 ma i ccs 5v cc 5v cc 5 = 5.0 v ? 15 20 ma *2 i ccs 3v cc 3v cc 3 = 3.0 v ? 24 85 ma i cch 5v cc 5 v cc 5 = 5.0 v, t a = 25 c ? 10 100 m a*3 i cch 3v cc 3 v cc 3 = 3.0 v, t a = 25 c ? 10 100 m a power current (flash models) i cc 3v cc 3v cc 3 = 3.3 v ? 80 120 ma i ccs 3v cc 3v cc 3 = 3.3 v ? 50 90 ma input capacity c in other than v cc , av cc , av ss , av rh and v ss ?? 10 ? pf
mb91133/mb91f133 91 4. ac characteristics (1) clock timing standard (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) *1 : frequency fluctuation rate indicates the maximum fluctuation ratio from the setting central frequency during locking in case of doubling. *2 : the targeted analog areas are the a/d and level comparator. parameter sym- bol pin name condi- tions value unit remarks min. max. clock frequency (high-speed, self-oscillation) f c x0, x1 ? 9 16.5 mhz self oscillation available area clock frequency (high-speed, pll usage) pll usable area by self-oscillation input clock frequency (low-speed) f ca x0a, x1a 32 khz self oscillation clock cycle time t c ? 30.3 31250 ns frequency fluctuation rate *1 (when pll locked) d f ?? 10 % internal operation clock frequency cpu system f cp ? ? 0.032 33 mhz bus system f cpb 0.032 25 peripheral system f cpp 0.032 25 excluding analog area *2 1 25 analog area *2 internal operation clock cycle time cpu system t cp ? 30.3 31250 ns bus system t cpb 40 31250 peripheral system t cpp 40 31250 excluding analog area *2 40 1000 analog area *2
mb91133/mb91f133 92 -a -a central frequency f o t c v cc 3 v ss 0.8 v cc 3 0.2 v cc 3 d f = 100 ( % ) | a | f o v cc 3 3.6 3.0 f cpp f cp 1 m frequency (hz) guaranteed operating range power voltage (v) 33 m 32 k 25 m peripheral system clock setting permitted area (a/d, d/a level comparator : 5 v 10 % ) < flash model > v cc 3 3.6 2.7 f cpp f cp 1 m 33 m 32 k 25 m frequency (hz) guaranteed operating range power voltage (v) < mask rom model >
mb91133/mb91f133 93 the relationship between the internal clock set by the chc/cck1/cck0 bit of the gear control register (gcr) and x0 input is as follows. t cyc t cyc t cyc t cyc t cyc t cyc t cyc t cyc x0 input original oscillation 1 (chc bit of gcr : 0 setting) (a) gear 1 internal clock cck1/0 : 00 (b) gear 1/2 internal clock cck1/0 : 01 (c) gear 1/4 internal clock cck1/0 : 10 (d) gear 1/8 internal clock cck1/0 : 11 original oscillation 1/2 (chc bit of gcr : 1 setting) (a) gear 1 internal clock cck1/0 : 00 (b) gear 1/2 internal clock cck1/0 : 01 (c) gear 1/4 internal clock cck1/0 : 10 (d) gear 1/8 internal clock cck1/0 : 11
mb91133/mb91f133 94 (2) reset input standards (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (3) power on reset (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) parameter symbol pin name condi- tions value unit remarks min. max. reset input time t rstl rst ? t cp 5 ? ns parameter sym- bol pin name conditions value unit remarks min. max. power startup time f r v cc ? ? 20 ms power cut time t off 2 ? ms waiting time for oscillation stabilization t osc ? 2 13 t c ? ns rst t rstl 0.2 v cc v hhr t r 0.9 v cc 3 0.2 v t off v cc v ss v cc rst t rstl holding ram data t osc (waiting for oscillation stabilization) if the power voltage is changed rapidly, power on reset may be initiated. to start up smoothly, controlling any voltage fluctuations that may occur during operation is recommended. controling inclination at initiation to 50 mv/ms or less is recommended. when power is turned on, start while the rst pin is set to l level, after which wait for t rstl minutes and change the level to h once the v cc power level is reached.
mb91133/mb91f133 95 (4) serial i/o (ch0 to 4) (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) *: will be min. 1 t cpp - 10 if pre-scalar setting is cs2, 1, 0 = 000. parameter symbol pin name conditions value unit remarks min. max. serial clock cycle time t scyc ? internal clock 8 t cpp ? ns sck ? so delay time t slov ?- 10 50 ns valid si ? sck - t ivsh ? 50 ? ns sck - ? valid si holding time t shix ? 50 ? ns serial clock h pulse width t shsl ? external clock 4 t cpp - 10 ? ns * serial clock l pulse width t slsh ? 4 t cpp - 10 ? ns sck ? so delay time t slov ? 050ns valid si ? sck - t ivsh ? 50 ? ns sck - ? valid si holding time t shix ? 50 ? ns serial busy period t busy ?? 6 t cpp ns scs ? sck, so delay time t clzo ?? 50 ns scs ? sck input mask time t clsl ?? 3 t cpp ns scs - ? sck, so hi-z time t choz ? 50 ? ns internal shift clock mode external shift clock mode sck so si t shix t ivsh t slov t scyc sck so si scs t choz t busy t clsl t ivsh t shix t slov t slsh t clzo t shsl
mb91133/mb91f133 96 (5) external bus measurement conditions the following conditions apply to items without specific regulations. ? alternating current standard measurement condition v cc : 5.0 v 10 % ? load condition ? load capacity - delay time characteristic (internally-based output delay) v ih v il v oh v ol v cc input output 0 v (rise/fall time of input is 10 ns or less) v ih 2.4 v v oh 2.4v v il 0.8 v v ol 0.8v c = 50 pf ( v cc : 5.0 v 10% ) output pin [ns] 35 30 25 20 15 10 5 0 0 20 40 50 60 80 100 120 c[pf] 5 v rise 5 v fall
mb91133/mb91f133 97 (6) normal bus access read/write operation (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) *1 : time (t cyc number of cycles extended) needs to be added to this standard if the bus is extended by automatic waiting insertion and rdy input. *2 : values of this standard are in case of gear cycle 1. if the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. calculation formula : (2 - n / 2) t cyc - 25 parameter sym- bol pin name conditions value unit remarks min. max. address delay time t chav clk a23 to a00 ? ? 15 ns data delay time t chdv clk d31 to d16 ? 15 ns rd delay time t clrl clk rd ? 10 ns rd delay time t clrh ? 10 ns wr0 to 1 delay time t clwl clk wr0 to 1 ? 10 ns wr0 to 1 delay time t clwh ? 10 ns valid address / valid data input time t avdv a23 to a00 d31 to d16 ? 3 / 2 t cyc - 25 ns *1, *2 rd ? valid data input time t rldv rd d31 to d16 ? t cyc - 15 ns *1 data setup ? rd - time t dsrh 15 ? ns rd - ? data holding time t rhdx 0 ? ns
mb91133/mb91f133 98 t cyc t chav t clrl t clrh t rldv t avdv t rhdx ba1 ba2 v oh v ol v oh v ol v oh v ol v oh v ol v ol v il v ih read write v il v ih v oh t dsrh v oh v ol v oh v ol v oh v ol t clwh t clwl t chdv clk a24 - a00 rd d31 - d16 wr0 - wr1 d31 - d16
mb91133/mb91f133 99 (7) ready input timing (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) parameter symbol pin name conditions value unit remarks min. max. rdy setup time ? clk t rdys rdy clk ? 15 ? ns clk ? rdy holding time t rdyh rdy clk 0 ? ns clk rdy if "wait" is executed rdy if "wait" is not executed v ih v il v oh v oh v ol v ol v ih v il t rdyh t rdys t rdyh t rdys t cyc
mb91133/mb91f133 100 (8) holding timing (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) note : it takes at least one cycle from loading the brq to when bgrnt is changed. parameter symbol pin name conditions value unit remarks min. max. bgrnt delay time t chbgl clk bgrnt ? ? 6ns bgrnt delay time t chbgh ? 6ns pin floating ? bgrnt time t xhal bgrnt t cyc - 10 t cyc + 10 ns bgrnt - ? pin valid time t hahv t cyc - 10 t cyc + 10 ns v ol v oh t chbgl t xhal high impedance t hahv t chbgh tcyc brq bgrnt each pin clk v oh v oh v oh v oh
mb91133/mb91f133 101 (9) dma controller timing (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) parameter symbol pin name conditions value unit remarks min. max. dreq input pulse width t drwh dreq0 to dreq2 ? 2 t cyc ? ns dack delay time (normal bus) t cldl clk dack0 to dack2 ? 6ns t cldh ? 6ns eop delay time (normal bus) t clel clk eop0 to eop2 ? 6ns t cleh ? 6ns dack delay time t chdl clk dack0 to dack2 ? n / 2 t cyc ns t chdh ? 6ns eop delay time t chel clk eop0 to eop2 ? n / 2 t cyc ns t cheh ? 6ns clk v ol v ol v oh v oh v ih v ih t clel t cldl t cleh t cldh t chdh t chdl t chel t drwh v oh v ol v ol v oh tcyc dack0 - 2 eop0 - 2 (normal bus) dack0 - 2 eop0 - 2 dreq0 - 2
mb91133/mb91f133 102 5. a/d transition (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) notes : as the |av rh | becomes smaller, the tolerance becomes larger. output impedance of external circuits other than analog input must be used if output impedance of external circuits < approx. 7 k w if the output impedance of the external circuits is too high, the sampling time for the analog voltage may be insufficient. (sampling time = 1.6 m s at 33 mhz) parameter sym- bol pin name conditions value unit re- marks min. typ. max. resolution ?? ? ?? 10 bit conversion time ?? 5.0 ?m s total tolerance ?? av cc = 5.0 v, av rh = 5.0 v - 4.0 ? 4.0 lsb straight-line tolerance ?? - 3.5 ? 3.5 lsb differential straight-line tolerance ?? - 2.0 ? 2.0 lsb zero transition tolerance v ot an0 to an7 av cc = 5.0 v, av rh = 5.0 v av ss - 1.5 av ss + 0.5 av ss + 2.5 lsb full-scale transition tolerance v fst an0 to an7 av rh - 5.5 av rh - 1.5 av rh + 0.5 lsb analog input current i ain an0 to an7 ? ? 0.1 10 m a analog input voltage v ain an0 to an7 av ss ? av rh v standard voltage av rh av rh ??? av cc v power current when conversion is activated i a av cc av cc = 5.0 v ? 3.0 5.0 ma when conversion is stopped i ah ?? 5.0 m a standard voltage current supplied when conversion is activated i r av rh av cc = 5.0 v, av rh = 5.0v ? 2.0 3.0 ma when conversion is stopped i rh ?? 10 m a tolerance between channels ? an0 to an7 ??? 4lsb
mb91133/mb91f133 103 ? definition of a/d converter terms ? resolution : analog changes that can be identified by a/d converter ? straight-line tolerance : difference between the straight line linking the zero transition point (00 0000 0000 ?? 00 0000 0001) to the full-scale transition point (11 1111 1110 ?? 11 1111 1111) and actual conversion characteristics. ? differential straight-line tolerance : difference compared to the ideal input voltage value required to change the output code 1 lsb ? total tolerance : indicates the difference between the actual and theoretical values and includes zero transition tolerance, full- scale transition tolerance, and straight-line tolerance. (continued) 3ff 3fe 3fd 004 003 002 001 av ss avrh analog input 0.5 lsb { 1 lsb ( n - 1 ) + 0.5 lsb } 1.5 lsb ideal characteristics actual conversion characteristics actual conversion characteristics digital output v nt (actual measured value) total tolerance total tolerance of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb 1 lsb (ideal value) = avrh - av ss 1024 [v] v ot (ideal value) = av ss + 0.5 lsb v nt : voltage of digital output transferred from (n + 1) to n [v] v fst (ideal value) = avrh - 1.5 lsb [v]
mb91133/mb91f133 104 (continued) 6. d/a transition (mask model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) (flash model v cc 5 = av cc = davc = 5.0 v 10 % , v cc 3 = 3.0 v to 3.6 v, v ss = av ss = 0 v, t a = - 40 c to + 70 c) *: cl = 20 pf parameter symbol pin name condi- tions value unit re- marks min. typ. max. resolution ??? ? ? 8bit differential straight-line tolerance ??? ? ? 0.9 lsb conversion time ??? ? 10 20 m s* analog output impedance ??? ? 28 ? k w straight-line tolerance of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential straight-line tolerance of digital output n = v ( n + 1 ) t - v nt 1 lsb - 1 1lsb (ideal value) = v fst - v ot 1022 [v] v ot : voltage with digital output transferred from (000) h to (001) h v fst : voltage with digital output transferred from (3fe) h to (3ff) h [lsb] 3ff 3fe 3fd 004 003 002 001 av ss avrh { 1 lsb ( n - 1 ) + v ot } analog input ideal characteristics actual conversion characteristics actual conversion characteristics digital output v nt (actual measured value) v fst (actual measured value) v ot (actual measured value) n + 1 n n - 1 n - 2 av ss avrh analog input ideal characteristics actual conversion characteristics actual conversion characteristics digital output v nt (actual measured value) v fst (actual measured value) straight-line tolerance differential straight-line tolerance
mb91133/mb91f133 105 n n n n instructions (165 instructions) 1. how to read instruction set summary (1) names of instructions instructions marked with * are not included in cpu specifications. these are extended instruction codes added/extended at assembly language levels. (2) addressing modes specified as operands are listed in symbols. refer to 2. addressing mode symbols for further information. (3) instruction types (4) hexa-decimal expressions of instructions (5) the number of machine cycles needed for execution a: memory access cycle and it has possibility of delay by ready function. b: memory access cycle and it has possibility of delay by ready function. if an object register in a ld operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: if an immediately following instruction operates to an object of r15, ssp or usp in read/write mode or if the instruction belongs to instruction format a group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: if an immediately following instruction refers to mdh/mdl, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. for a, b, c and d, minimum execution cycle is 1. (6) change in flag sign ? flag change c : change C : no change 0:clear 1:set ? flag meanings n : negative flag z:zero flag v:over flag c:carry flag (7) operation carried out by instruction mnemonic type op cyc nzvc operation remarks add rj, ri * add #s5, ri , , a c , , a6 a4 , , 1 1 , , cccc cccc , , ri + rj ? ri ri + s5 ? ri , , (1) (2) (3) (4) (5) (6) (7)
mb91133/mb91f133 106 2. addressing mode symbols ri : register direct (r0 to r15, ac, fp, sp) rj : register direct (r0 to r15, ac, fp, sp) r13 : register direct (r13, ac) ps : register direct (program status register) rs : register direct (tbr, rp, ssp, usp, mdh, mdl) cri : register direct (cr0 to cr15) crj : register direct (cr0 to cr15) #i8 : unsigned 8-bit immediate (C128 to 255) note: C128 to C1 are interpreted as 128 to 255 #i20 : unsigned 20-bit immediate (C0x80000 to 0xfffff) note: C0x7ffff to C1 are interpreted as 0x7ffff to 0xfffff #i32 : unsigned 32-bit immediate (C0x80000000 to 0xffffffff) note: C0x80000000 to C1 are interpreted as 0x80000000 to 0xffffffff #s5 : signed 5-bit immediate (C16 to 15) #s10 : signed 10-bit immediate (C512 to 508, multiple of 4 only) #u4 : unsigned 4-bit immediate (0 to 15) #u5 : unsigned 5-bit immediate (0 to 31) #u8 : unsigned 8-bit immediate (0 to 255) #u10 : unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : unsigned 8-bit direct address (0 to 0xff) @dir9 : unsigned 9-bit direct address (0 to 0x1fe, multiple of 2 only) @dir10 : unsigned 10-bit direct address (0 to 0x3fc, multiple of 4 only) label9 : signed 9-bit branch address (C0x100 to 0xfc, multiple of 2 only) label12 : signed 12-bit branch address (C0x800 to 0x7fc, multiple of 2 only) label20 : signed 20-bit branch address (C0x80000 to 0x7ffff) label32 : signed 32-bit branch address (C0x80000000 to 0x7fffffff) @ri : register indirect (r0 to r15, ac, fp, sp) @rj : register indirect (r0 to r15, ac, fp, sp) @(r13, rj) : register relative indirect (rj: r0 to r15, ac, fp, sp) @(r14, disp10) : register relative indirect (disp10: C0x200 to 0x1fc, multiple of 4 only) @(r14, disp9) : register relative indirect (disp9: C0x100 to 0xfe, multiple of 2 only) @(r14, disp8) : register relative indirect (disp8: C0x80 to 0x7f) @(r15, udisp6) : register relative (udisp6: 0 to 60, multiple of 4 only) @ri+ : register indirect with post-increment (r0 to r15, ac, fp, sp) @r13+ : register indirect with post-increment (r13, ac) @sp+ : stack pop @Csp : stack push (reglist) : register list
mb91133/mb91f133 107 3. instruction types add, addn, cmp, lsl, lsr and asr instructions only msb ty p e a ri lsb rj op ty p e b ty p e c ty p e * c ty p e d ty p e e ty p e f 16 bits 4 4 8 op i8/o8 ri 484 ri u4/m4 op 4 4 8 op s5/u5 ri 754 op u8/rel8/dir/reglist 88 op sub-op ri 844 op rel11 511
mb91133/mb91f133 108 4. detailed description of instructions ? add/subtract operation instructions (10 instructions) ? compare operation instructions (3 instructions) ? logical operation instructions (12 instructions) mnemonic type op cycle n z v c operation remarks add rj, ri * add #s5, ri add #i4, ri add2 #i4, ri a c c c a6 a4 a4 a5 1 1 1 1 cccc cccc cccc cccc ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension addc rj, ri a a7 1 cccc ri + rj + c ? ri add operation with sign addn rj, ri * addn #s5, ri addn #i4, ri addn2 #i4, ri a c c c a2 a0 a0 a1 1 1 1 1 CCCC CCCC CCCC CCCC ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension sub rj, ri a ac 1 cccc ri C rj ? ri subc rj, ri a ad 1 cccc ri C rj C c ? ri subtract operation with carry subn rj, ri a ae 1 C C C C ri C rj ? ri mnemonic type op cycle n z v c operation remarks cmp rj, ri * cmp #s5, ri cmp #i4, ri cmp2 #i4, ri a c c c aa a8 a8 a9 1 1 1 1 cccc cccc cccc cccc ri C rj ri C s5 ri + extu (i4) ri + extu (i4) msb is interpreted as a sign in assembly language zero-extension sign-extension mnemonic type op cycle n z v c operation remarks and rj, ri and rj, @ri andh rj, @ri andb rj, @ri a a a a 82 84 85 86 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri & = rj (ri) & = rj (ri) & = rj (ri) & = rj word word half word byte or rj, ri or rj, @ri orh rj, @ri orb rj, @ri a a a a 92 94 95 96 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri | = rj (ri) | = rj (ri) | = rj (ri) | = rj word word half word byte eor rj, ri eor rj, @ri eorh rj, @ri eorb rj, @ri a a a a 9a 9c 9d 9e 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri ^ = rj (ri) ^ = rj (ri) ^ = rj (ri) ^ = rj word word half word byte
mb91133/mb91f133 109 ? bit manipulation arithmetic instructions (8 instructions) *1: assembler generates bandl if result of logical operation u8&0x0f leaves an active (set) bit and generates bandh if u8&0xf0 leaves an active bit. depending on the value in the u8 format, both bandl and bandh may be generated. *2: assembler generates borl if result of logical operation u8&0x0f leaves an active (set) bit and generates borh if u8&0xf0 leaves an active bit. *3: assembler generates beorl if result of logical operation u8&0x0f leaves an active (set) bit and generates beorh if u8&0xf0 leaves an active bit. ? add/subtract operation instructions (10 instructions) *1: divos, div1 32, div2, div3 and div4s are generated. a total instruction code length of 72 bytes. *2: divou and div1 32 are generated. a total instruction code length of 66 bytes. mnemonic type op cycle n z v c operation remarks bandl #u4, @ri (u4: 0 to 0f h ) bandh #u4, @ri (u4: 0 to 0f h ) * band #u8, @ri * 1 c c 80 81 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) & = (f0 h + u4) (ri) & = ((u4<<4) + 0f h ) (ri) & = u8 manipulate lower 4 bits manipulate upper 4 bits borl #u4, @ri (u4: 0 to 0f h ) borh #u4, @ri (u4: 0 to 0f h ) * bor #u8, @ri * 2 c c 90 91 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) | = u4 (ri) | = (u4<<4) (ri) | = u8 manipulate lower 4 bits manipulate upper 4 bits beorl #u4, @ri (u4: 0 to 0f h ) beorh #u4, @ri (u4: 0 to 0f h ) * beor #u8, @ri * 3 c c 98 99 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) ^ = u4 (ri) ^ = (u4<<4) (ri) ^ = u8 manipulate lower 4 bits manipulate upper 4 bits btstl #u4, @ri (u4: 0 to 0f h ) btsth #u4, @ri (u4: 0 to 0f h ) c c 88 89 2 + a 2 + a 0cCC ccC C (ri) & u4 (ri) & (u4<<4) te s t l o w e r 4 b i t s test upper 4 bits mnemonic type op cycle n z v c operation remarks mul rj, ri mulu rj, ri mulh rj, ri muluh rj, ri a a a a af ab bf bb 5 5 3 3 cccC cccC ccC C ccC C rj ri ? mdh, mdl rj ri ? mdh, mdl rj ri ? mdl rj ri ? mdl 32-bit 32-bit = 64-bit unsigned 16-bit 16-bit = 32-bit unsigned divos ri divou ri div1 ri div2 ri div3 div4s * div ri * 1 * divu ri * 2 e e e e e e 97 C 4 97 C 5 97 C 6 97 C 7 9f C 6 9f C 7 1 1 d 1 1 1 C C CCCC CCCC CcCc CcCc CCCC CCCC CcCc CcCc mdl/ri ? mdl, mdl%ri ? mdh mdl/ri ? mdl, mdl%ri ? mdh step calculation 32-bit/32-bit = 32-bit unsigned
mb91133/mb91f133 110 ? shift arithmetic instructions (9 instructions) ? immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) *1: if an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. if an immediate value contains relative value or external reference, assembler selects i32. ? memory load instructions (13 instructions) note: the relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 ? o8 = disp8:each disp is a code extension. disp9 ? o8 = disp9>>1:each disp is a code extension. disp10 ? o8 = disp10>>2:each disp is a code extension. udisp6 ? u4 = udisp6>>2:udisp4 is a 0 extension. mnemonic type op cycle n z v c operation remarks lsl rj, ri * lsl #u5, ri lsl #u4, ri lsl2 #u4, ri a c c c b6 b4 b4 b5 1 1 1 1 ccCc ccCc ccCc ccCc ri<>rj ? ri ri>>u5 ? ri ri>>u4 ? ri ri>>(u4 + 16) ? ri logical shift asr rj, ri * asr #u5, ri asr #u4, ri asr2 #u4, ri a c c c ba b8 b8 b9 1 1 1 1 ccCc ccCc ccCc ccCc ri>>rj ? ri ri>>u5 ? ri ri>>u4 ? ri ri>>(u4 + 16) ? ri logical shift mnemonic type op cycle n z v c operation remarks ldi: 32 #i32, ri ldi: 20 #i20, ri ldi: 8 #i8, ri * ldi # {i8 | i20 | i32}, ri * 1 e c b 9f C 8 9b c0 3 2 1 CCCC CCCC CCCC i32 ? ri i20 ? ri i8 ? ri {i8 | i20 | i32} ? ri upper 12 bits are zero- extended upper 24 bits are zero- extended mnemonic type op cycle n z v c operation remarks ld @rj, ri ld @(r13, rj), ri ld @(r14, disp10), ri ld @(r15, udisp6), ri ld @r15 +, ri ld @r15 +, rs ld @r15 +, ps a a b c e e e 04 00 20 03 07 C 0 07 C 8 07 C 9 b b b b b b 1 + a + b CCCC CCCC CCCC CCCC CCCC CCCC cccc (rj) ? ri (r13 + rj) ? ri (r14 + disp10) ? ri (r15 + udisp6) ? ri (r15) ? ri, r15 + = 4 (r15) ? rs, r15 + = 4 (r15) ? ps, r15 + = 4 rs: special-purpose register lduh @rj, ri lduh @(r13, rj), ri lduh @(r14, disp9), ri a a b 05 01 40 b b b CCCC CCCC CCCC (rj) ? ri (r13 + rj) ? ri (r14 + disp9) ? ri zero-extension zero-extension zero-extension ldub @rj, ri ldub @(r13, rj), ri ldub @(r14, disp8), ri a a b 06 02 60 b b b CCCC CCCC CCCC (rj) ? ri (r13 + rj) ? ri (r14 + disp8) ? ri zero-extension zero-extension zero-extension
mb91133/mb91f133 111 ? memory store instructions (13 instructions) note: the relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 ? o8 = disp8:each disp is a code extension. disp9 ? o8 = disp9>>1:each disp is a code extension. disp10 ? o8 = disp10>>2:each disp is a code extension. udisp6 ? u4 = udisp6>>2:udisp4 is a 0 extension. ? transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) mnemonic type op cycle n z v c operation remarks st ri, @rj st ri, @(r13, rj) st ri, @(r14, disp10) st ri, @(r15, udisp6) st ri, @Cr15 st rs, @Cr15 st ps, @Cr15 a a b c e e e 14 10 30 13 17 C 0 17 C 8 17 C 9 a a a a a a a CCCC CCCC CCCC CCCC CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp10) ri ? (r15 + usidp6) r15 C = 4, ri ? (r15) r15 C = 4, rs ? (r15) r15 C = 4, ps ? (r15) word word word rs: special-purpose register sth ri, @rj sth ri, @(r13, rj) sth ri, @(r14, disp9) a a b 15 11 50 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp9) half word half word half word stb ri, @rj stb ri, @(r13, rj) stb ri, @(r14, disp8) a a b 16 12 70 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp8) byte byte byte mnemonic type op cycle n z v c operation remarks mov rj, ri mov rs, ri mov ri, rs mov ps, ri mov ri, ps a a a e e 8b b7 b3 17 C 1 07 C 1 1 1 1 1 c CCCC CCCC CCCC CCCC cccc rj ? ri rs ? ri ri ? rs ps ? ri ri ? ps transfer between general-purpose registers rs: special-purpose register rs: special-purpose register
mb91133/mb91f133 112 ? non-delay normal branch instructions (23 instructions) notes: ? 2/1 in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? reti must be operated while s flag = 0. mnemonic type op cycle n z v c operation remarks jmp @ri e 97 C 0 2 CCCC ri ? pc call label12 call @ri f e d0 97 C 1 2 2 CCCC CCCC pc + 2 ? rp, pc + 2 + rel11 2 ? pc pc + 2 ? rp, ri ? pc ret e 97 C 2 2 C C C C rp ? pc return int #u8 d 1f 3+3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? i flag, 0 ? s flag, (tbr + 3fc C u8 4) ? pc inte e 9f C 3 3 + 3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? s flag, (tbr + 3d8 C u8 4) ? pc for emulator reti e 97 C 3 2 + 2a c c c c (r15) ? pc, r15 C = 4, (r15) ? ps, r15 C = 4 bno label9 bra label9 beq label9 bne label9 bc label9 bnc label9 bn label9 bp label9 bv label9 bnv label9 blt label9 bge label9 ble label9 bgt label9 bls label9 bhi label9 d d d d d d d d d d d d d d d d e1 e0 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0
mb91133/mb91f133 113 ? branch instructions with delays (20 instructions) notes: ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? delayed branch operation always executes next instruction (delay slot) before making a branch. ? instructions allowed to be stored in the delay slot must meet one of the following conditions. if the other instruction is stored, this device may operate other operation than defined. the instruction described 1 in the other cycle column than branch instruction. the instruction described a, b, c or d in the cycle column. mnemonic type op cycle n z v c operation remarks jmp:d @ri e 9f C 0 1 CCCC ri ? pc call:d label12 call:d @ri f e d8 9f C 1 1 1 CCCC CCCC pc + 4 ? rp, pc + 2 + rel11 2 ? pc pc + 4 ? rp, ri ? pc ret:d e 9f C 2 1 CCCC rp ? pc return bno:d label9 bra:d label9 beq:d label9 bne:d label9 bc:d label9 bnc:d label9 bn:d label9 bp:d label9 bv:d label9 bnv:d label9 blt:d label9 bge:d label9 ble:d label9 bgt:d label9 bls:d label9 bhi:d label9 d d d d d d d d d d d d d d d d f1 f0 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0
mb91133/mb91f133 114 ? direct addressing instructions note: the relations between the dir field of type-d in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 ? dir + disp8:each disp is a code extension disp9 ? dir = disp9>>1:each disp is a code extension disp10 ? dir = disp10>>2:each disp is a code extension ? resource instructions (2 instructions) ? co-processor instructions (4 instructions) mnemonic type op cycle n z v c operation remarks dmov @dir10, r13 dmov r13, @dir10 dmov @dir10, @r13+ dmov @r13+, @dir10 dmov @dir10, @Cr15 dmov @r15+, @dir10 d d d d d d 08 18 0c 1c 0b 1b b a 2a 2a 2a 2a CCCC CCCC CCCC CCCC CCCC CCCC (dir10) ? r13 r13 ? (dir10) (dir10) ? (r13), r13 + = 4 (r13) ? (dir10), r13 + = 4 r15 C = 4, (dir10) ? (r15) (r15) ? (dir10), r15 + = 4 word word word word word word dmovh @dir9, r13 dmovh r13, @dir9 dmovh @dir9, @r13+ dmovh @r13+, @dir9 d d d d 09 19 0d 1d b a 2a 2a CCCC CCCC CCCC CCCC (dir9) ? r13 r13 ? (dir9) (dir9) ? (r13), r13 + = 2 (r13) ? (dir9), r13 + = 2 half word half word half word half word dmovb @dir8, r13 dmovb r13, @dir8 dmovb @dir8, @r13+ dmovb @r13+, @dir8 d d d d 0a 1a 0e 1e b a 2a 2a CCCC CCCC CCCC CCCC (dir8) ? r13 r13 ? (dir8) (dir8) ? (r13), r13 + + (r13) ? (dir8), r13 + + byte byte byte byte mnemonic type op cycle n z v c operation remarks ldres @ri+, #u4 c bc a C C C C (ri) ? u4 resource ri + = 4 u4: channel number stres #u4, @ri+ c bd a C C C C u4 resource ? (ri) ri + = 4 u4: channel number mnemonic type op cycle n z v c operation remarks copop #u4, #cc, crj, cri copld #u4, #cc, rj, cri copst #u4, #cc, crj, ri copsv #u4, #cc, crj, ri e e e e 9f C c 9f C d 9f C e 9f C f 2 + a 1 + 2a 1 + 2a 1 + 2a CCCC CCCC CCCC CCCC calculation rj ? cri crj ? ri crj ? ri no error traps
mb91133/mb91f133 115 ? other instructions (16 instructions) *1: in the addsp instruction, the reference between u8 of type-d in the instruction format and assembler description s10 is as follows. s10 ? s8 = s10>>2 *2: in the enter instruction, the reference between i8 of type-c in the instruction format and assembler description u10 is as follows. u10 ? u8 = u10>>2 *3: if either of r0 to r7 is specified in reglist, assembler generates ldm0. if either of r8 to r15 is specified, assembler generates ldm1. both ldm0 and ldm1 may be generated. *4: the number of cycles needed for execution of ldm0 (reglist) and ldm1 (reglist) is given by the following calculation; a (n C 1) + b + 1 when n is number of registers specified. *5: if either of r0 to r7 is specified in reglist, assembler generates stm0. if either of r8 to r15 is specified, assembler generates stm1. both stm0 and stm1 may be generated. *6: the number of cycles needed for execution of stm0 (reglist) and stm1 (reglist) is given by the following calculation; a n + 1 when n is number of registers specified. mnemonic type op cycle n z v c operation remarks nop e 9f C a 1 C C C C no changes andccr #u8 orccr #u8 d d 83 93 c c cccc cccc ccr and u8 ? ccr ccr or u8 ? ccr stilm #u8 d 87 1 CCCC i8 ? ilm set ilm immediate value addsp #s10 * 1 d a3 1 CCCC r15 + = s10 add sp instruction extsb ri extub ri extsh ri extuh ri e e e e 97 C 8 97 C 9 97 C a 97 C b 1 1 1 1 CCCC CCCC CCCC CCCC sign extension 8 ? 32 bits zero extension 8 ? 32 bits sign extension 16 ? 32 bits zero extension 16 ? 32 bits ldm0 (reglist) ldm1 (reglist) * ldm (reglist) * 3 d d 8c 8d * 4 * 4 C CCCC CCCC CCCC (r15) ? reglist, r15 increment (r15) ? reglist, r15 increment (r15 + +) ? reglist, load-multi r0 to r7 load-multi r8 to r15 load-multi r0 to r15 stm0 (reglist) stm1 (reglist) * stm2 (reglist) * 5 d d 8e 8f * 6 * 6 C CCCC CCCC CCCC r15 decrement, reglist ? (r15) r15 decrement, reglist ? (r15) reglist ? (r15 + +) store-multi r0 to r7 store-multi r8 to r15 store-multi r0 to r15 enter #u10 * 2 d 0f 1+a CCCC r14 ? (r15 C 4), r15 C 4 ? r14, r15 C u10 ? r15 entrance processing of function leave e 9f C 9 b C C C C r14 + 4 ? r15, (r15 C 4) ? r14 exit processing of function xchb @rj, ri a 8a 2a C C C C ri ? temp, (rj) ? ri, temp ? (rj) for semafo management byte data
mb91133/mb91f133 116 ? 20-bit normal branch macro instructions *1: call20 (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call @ri *2: bra20 (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp @ri *3: bcc20 (beq20 to bhi20) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp @ri false: mnemonic operation remarks * call20 label20, ri next instruction address ? rp, label20 ? pc ri: temporary register * 1 * bra20 label20, ri * beq20 label20, ri * bne20 label20, ri * bc20 label20, ri * bnc20 label20, ri * bn20 label20, ri * bp20 label20, ri * bv20 label20, ri * bnv20 label20, ri * blt20 label20, ri * bge20 label20, ri * ble20 label20, ri * bgt20 label20, ri * bls20 label20, ri * bhi20 label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
mb91133/mb91f133 117 ? 20-bit delayed branch macro instructions *1: call20:d (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call:d @ri *2: bra20:d (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp:d @ri *3: bcc20:d (beq20:d to bhi20:d) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp:d @ri false: mnemonic operation remarks * call20:d label20, ri next instruction address + 2 ? rp, label20 ? pc ri: temporary register * 1 * bra20:d label20, ri * beq20:d label20, ri * bne20:d label20, ri * bc20:d label20, ri * bnc20:d label20, ri * bn20:d label20, ri * bp20:d label20, ri * bv20:d label20, ri * bnv20:d label20, ri * blt20:d label20, ri * bge20:d label20, ri * ble20:d label20, ri * bgt20:d label20, ri * bls20:d label20, ri * bhi20:d label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
mb91133/mb91f133 118 ? 32-bit normal macro branch instructions *1: call32 (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call @ri *2: bra32 (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp @ri *3: bcc32 (beq32 to bhi32) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp @ri false: mnemonic operation remarks * call32 label32, ri next instruction address ? rp, label32 ? pc ri: temporary register * 1 * bra32 label32, ri * beq32 label32, ri * bne32 label32, ri * bc32 label32, ri * bnc32 label32, ri * bn32 label32, ri * bp32 label32, ri * bv32 label32, ri * bnv32 label32, ri * blt32 label32, ri * bge32 label32, ri * ble32 label32, ri * bgt32 label32, ri * bls32 label32, ri * bhi32 label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
mb91133/mb91f133 119 ? 32-bit delayed macro branch instructions *1: call32:d (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call:d @ri *2: bra32:d (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp:d @ri *3: bcc32:d (beq32:d to bhi32:d) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp:d @ri false: mnemonic operation remarks * call32:d label32, ri next instruction address + 2 ? rp, label32 ? pc ri: temporary register * 1 * bra32:d label32, ri * beq32:d label32, ri * bne32:d label32, ri * bc32:d label32, ri * bnc32:d label32, ri * bn32:d label32, ri * bp32:d label32, ri * bv32:d label32, ri * bnv32:d label32, ri * blt32:d label32, ri * bge32:d label32, ri * ble32:d label32, ri * bgt32:d label32, ri * bls32:d label32, ri * bhi32:d label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
mb91133/mb91f133 120 n ordering information part number package remarks mb91133pmt2-xxx 144-pin plastic lqfp (fpt-144p-m08) mb91133pbt-xxx 144-pin plastic fbga (bga-144p-m01) mb91f133pmt2 144-pin plastic lqfp (fpt-144p-m08) mb91f133pbt 144-pin plastic fbga (bga-144p-m01) MB91FV130CR-ES 299-pin ceramic pga (pga-299)
mb91133/mb91f133 121 n package dimensions 144-pin plastic fbga (bga-144p-m01) note) corner shape may differ from the diagram. dimensions in mm (inches) c 1998 fujitsu limited b144001s-2c-2 12.00?.10(.472?004)sq .049 ?004 +.008 ?.10 +0.20 1.25 (mounting height) 0.38?.10(.015?004) (stand off) 0.10(.004) c0.80(.031) index 10.40(.409)ref 0.80(.031)typ 1 2 3 4 5 6 7 8 9 10 11 lkjhgfedcba 144-0.45?.10 (144-.018?004) m 0.08(.003) 12 13 m n p 14
mb91133/mb91f133 122 144-pin plastic lqfp (fpt-144p-m08) dimensions in mm (inches) c 1995 fujitsu limited f144019s-1c-2 details of "a" part details of "b" part 0.500.20(.020.008) 0 10? 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 22.000.30(.866.012)sq 20.000.10(.787.004)sq 0.200.10 (.008.004) 0.08(.003) m 0.150.05 (.006.002) 1.70(.67)max 0(0)min (stand off) 21.00 17.50 (.827) nom (.686) ref 0.10(.004) "a" "b" 36 37 72 73 108 109 144 1 index 0.50(.0197)typ lead no.
mb91133/mb91f133 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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